基础工艺流程

基础工艺流程

200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors

  • Application, features: Small -scale integration analogue IC, <br /><br />VDD <  210 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn =70 Uсе=50 V<br /><br />NDMOS: Vtn= 2.0 V,<br /><br />Usd >200 V<br /><br />PDMOS: Vtp= -1.0 V,<br /><br />Usd >200 V<br /><br />NMOS: Vtn= 1.5V, Usd >20V<br /><br /> <br /><br />Resistors in layer:<br /><br />NPN base, Р-drain, PolySi.<br /><br /> <br /><br />Capacitors: PolySi-Si (SiO2 900 Å)<br /><br />PolySi-Al (SiO2 1600 Å)
  • Process Description: Number of masks, pcs.                                            19<br /><br />Min design rule,µm                                             4.0<br /><br />Substrate:        Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers:            Si/Sb-doped/ n-type/Thk 30/Res 5.5;<br /><br />                                  Si/B-doped/ p-type/Thk 300/Res2.0 ; <br /><br />Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0;<br /><br />Isolation:                                                    p-n junction<br /><br />P-well depth, µm                                                      6.5<br /><br />NDMOS base depth, µm                                          3.0<br /><br />Gate SiO2, Å                                                           900<br /><br />NPN p-base depth, µm                                             2.5<br /><br />N+emitter depth, µm                                                0.8<br /><br />Interlayer dielectric –  medium temp. PSG<br /><br />0,55mm +SIPOS 0.1µm + medium temp. PSG    1,1µm<br /><br />Channel length (gate):<br /><br />N/PDMOS, µm                                                            6                                            <br /><br />Space line PolySi, µm                                                 8<br /><br />Contacts, µm                                                             Ø4<br /><br />Space line Me, µm                                                      12

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers

  • Application, features: IC for telephony, customized IC,<br /><br />VDD 3 V… 5  V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >10 V<br /><br />PMOS: Vtр=-0.7 V, Usd >10 V
  • Process Description: Number of masks, pcs.                                   14 (16)<br /><br />Design rule,µm                                                    0.8<br /><br />Substrate:                        Si/ P-doped/n-type/Res 4.5<br /><br />                     or  Si/B-doped/ p-type/Res 12; 2 wells<br /><br />N/P-wells depth, µm                                           4/4<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PE (TEOS)                          1,05 µm<br /><br />Gate SiO2, Å                                                 130/160<br /><br />NMOS/PMOS channel length, µm                 0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                                    Ti/AlCu/Ti/TiN<br /><br />Space line PolySi,µm                                           1.9<br /><br />Contacts 1 (filled in by W), µm                         Ø 0.7<br /><br />Space line Me 1, µm                                             2.2<br /><br />Me2                                                               Ti/AlCu<br /><br />Contacts 2 (filled in by W),µm                        Ø 0.7<br /><br />Space line Me 2, µm                                             2.4

5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers

  • Application, features: Medium-scale integration EEPROM, VDD:2,4 V… 6  V<br /><br /> <br /><br />NMOS: Vtn=(0,65+-0,25)V, <br /><br />Usd >=12 V<br /><br />PMOS: Vtр=-(0,8+-0,2)V,<br /><br />Usd ≤-12 V<br /><br /> <br /><br />HV- NMOS: Vtn=(0,45+0,15)V Usd³17 V<br /><br />HV- РMOS: Vtр=-(0,8+0,2)V    Usd ≤-16 V
  • Process Description: Number of masks, pcs.                                             17<br /><br />Design rule, µm                                                       1.6<br /><br />Substrate: Si/B-doped/p-type/Res 12               2 wells                            <br /><br />N/P-well depth, µm                                                 5/6<br /><br />Gate SiO2, Å                                                          425<br /><br />Tunnel SiO2, Å                                                       77<br /><br />Interlayer dielectric-1: Si3N4, Å                            350<br /><br />Interlayer dielectric -2: BPSG, Å                           7000<br /><br />Built-in transistors<br /><br />Channel length: NMOS/PMOS<br /><br />Low-voltage transistors, µm                                     2.4<br /><br />High- voltage transistors, µm                                    3.6<br /><br />Space line PolySi 1, µm                                           3.2     <br /><br />Space line PolySi 2, µm                                           4.2<br /><br />Contacts, mm                                                        Ø 1.2<br /><br />Space line Me, µm                                                   4.4

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

  • Application, features: Digital IC, highly-resistant,<br />Epitaxy = 3 V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >5 V<br /><br />PMOS: Vtр=-0.6 V, Usd >5 V
  • Process Description: Number of photolithographies, pcs.               15<br /><br />Design rule, μm                                        0.35<br /><br />Substrate:                           725KDB0,015(100)<br /><br />Epitaxial layer:                                  15KDB12<br /><br />2 retrograde wells<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm             1.05 μm<br /><br />Gate SiO2, Å                                              70<br /><br />Channel length<br /><br />NMOS/PMOS, μm                                   0.35<br /><br />N&amp;P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I                                   Ti/AlCu / Ti /TiN<br /><br />PolySi pitch, μm                                       0.8<br /><br />Contacts 1 (W-filled), μm                        ø 0.5<br /><br />Metal 1 pitch, μm                                    0.95<br /><br />Metal 2                                              Ti/AlCu<br /><br />Contacts 2 (W-filled), μm                        ø 0.5<br /><br />Metal 2 pitch, μm                                      1.1

Bipolar technology for the manufacture of high-power npn-transistors with operating voltage of 1500 V

  • Application, features: UCE = 1500 V<br /><br /> UCE = (700-800) V<br /><br /> Ic= (5-12) A
  • Process Description: Substrate:                                    Si/ P-irradiated  /Res 102- 90<br /><br />8 masks (contact):<br /><br />Base: ion implantation depth, µm                                     20-26<br /><br />Emitter : diffusion, depth, µm                                             10-15<br /><br />collector-base p-n junction protection :                          SiPOS<br /><br />Metallization :                                                            Al      4, 5 µm<br /><br />Radiation treatment to ensure dynamics<br /><br />Backside matting<br /><br />Backside:                                                         Ti-Ni-Ag sputtering  

BiCDMOS, LOCOS isolation, 1 PolySi, 1 Me, NMOS/PMOS transistors

  • Application, features: Low-voltage transistors:<br /><br />NMOS: Vtn= 1.8 V, Usd >16 V<br /><br />PMOS: Vtp= 1.5 V, Usd >16 V<br /><br />NPN: h21e= 100-300<br /><br />Resistors in layer:<br /><br />PolySi 1= 20-30 Ohm/sq<br /><br /> <br /><br />High-voltage transistors :<br /><br />NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V<br /><br />PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V
  • Process Description: Number of masks, pcs.                                             15<br /><br />Min design rule,µm                                             2.8<br /><br />Substrate:                                   Si/B-doped/ p-type/ Res 80<br /><br />Isolation:                                                                   LOCOS<br /><br />P-well depth, µm                                                     6.5<br /><br />N-well depth, µm                                                     4.5<br /><br />NDMOS base depth, µm                                         2.4<br /><br />Gate SiO2, Å                                                           600<br /><br />Interlayer dielectric – Medium temp. PSG, µm       0,6                           <br /><br />Channel length (gate): N/PMOS, µm                     2.0<br /><br />Contacts, µm                                                    2.0x2.0<br /><br />Space line Me 1, µm                                                 8<br /><br />Space line Me 2, µm                                                10

5 V, 1.5 µm CMOS, 1 PolySi, 1 Ме, PolySi- resistors, 150mm wafers

  • Application, features: Supply voltage controllers <br /><br />NMOS:<br /><br />Vtn= 0.5 V, Usd >10 V<br /><br />PMOS:<br /><br />Vtp= 0.5V, Usd >10 V
  • Process Description: Number of masks, pcs.                                      17<br /><br />Design rule,µm                                                   1.5<br /><br />Substrate:      Si/B-doped/p-type/Res 12;      2 wells                   <br /><br />N/P-well depth, µm                                              5/6<br /><br />P-type PolySi resistors<br /><br />Bipolar vertical NPN transistor<br /><br />Gate SiO2, Å                                                       250<br /><br />Interlayer dielectric:                                       BPSG<br /><br />Channel length: NMOS/PMOS, µm                   1.7<br /><br />N&amp;P LDD- drains<br /><br />Space line PolySi, µm                                          2.5<br /><br />Contacts, µm                                                     Ø 1.3<br /><br />Space line Me, µm                                                3.5

5 V, 1.2 µm CMOS, 2 PolySi, 2 Me, low voltage EEPROM, 150 mm wafers

  • Application, features: LSI EEPROM, VDD:2,4 V… 6  V<br /><br />LV NMOS: Vtn=(0.4-0,8)V,  Usd>=12 V<br /><br />LV PMOS: Vtр=-(0.5-0,9)V,<br /><br />Usd ≤-12 V<br /><br />HV- NMOS: Vtn=(0,3-0,6)V, Usd>=17 V<br /><br />HV- РMOS: Vtр=-(0,6-1,0)V,<br /><br />Usd ≤-15 V
  • Process Description: Number of masks, pcs.                                                3<br /><br />(marked)<br /><br />Design rule, µm                                                         1.2<br /><br />Substrate:               Si/B-doped/ p-type/Res 12, 2 wells                 <br /><br />N/P-well depth, µm                                                    5/6<br /><br />Gate SiO2:<br /><br />Low voltage transistors, Å                                         250<br /><br />High voltage transistors, Å                                        350<br /><br />Tunnel SiO2, Å                                                          77<br /><br />Interlayer dielectric-1: Si3N4, Å                               350<br /><br />Interlayer dielectric -2: BPSG, Å                             7000<br /><br />Interlevel dielectric: PEoxide+SOG+ PEoxide<br /><br />Channel length:<br /><br />Low voltage NMOS/PMOS, µm                             1.4/1.6<br /><br />High voltage NMOS/PMOS, µm                            2.6/2.6<br /><br />N &amp; P LDD- drains<br /><br />Built-in transistors<br /><br />Space line PolySi 1, µm                                                 3.2     <br /><br />Space line PolySi 2, contact free, µm                            2.4<br /><br />Space line PolySi 2, with contact, µm                           4,6<br /><br />Contacts-1, µm                                                          Ø 1.2<br /><br />Space line  Me 1, contact free, µm                               3.2<br /><br />Space line Me 2, with contact, µm                               4,4<br /><br />Contacts 2, µm                                                         Ø 1.4<br /><br />Space line Me 2, contact free, µm                                4.4<br /><br />Space line Me 2, with contact, µm                                4,8

CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer

  • Application, features: Digital IC,<br /><br />Epitaxy =2.4¸6.0 V<br /><br /> <br /><br />For 3.0 V<br /><br />NMOS: Vtn=0.6 V, Usd >5 V<br /><br />PMOS: Vtр=-0.6 V, Usd >5 V<br /><br />For 5.0 V<br /><br />NMOS: Vtn=1.0 V, Usd >8 V<br /><br />PMOS: Vtр=-0.9 V, Usd >8 V
  • Process Description: Number of photolithographies, pcs.            22<br /><br />Design rule, μm                                        0.35<br /><br />Substrate:                         725KDB0,015(100)<br /><br />Epitaxial layer:                                15KDB12<br /><br />2 retrograde wells for high-voltage transistors<br /><br />2 retrograde wells for low-voltage transistors<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm        1.05 μm<br /><br />Gate SiO2, Å    70 for low-voltage transistors<br /><br />                        350 for high-voltage transistors<br /><br />Channel length<br /><br />NMOS/PMOS, μm     0.35 for low-voltage<br /><br />                                    transistors<br /><br />NMOS/PMOS, μm     1.0 for high-voltage<br /><br />                                    transistors                                               <br /><br />N&amp;P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I,2                                Ti/AlCu / Ti /TiN<br /><br />Contacts 1 (W-filled), μm                        ø 0.4<br /><br />Metal 1 pitch, μm                                    0.95<br /><br />Metal                                                  Ti/AlCu<br /><br />Contacts 2,3 (W-filled), μm                      ø 0.5<br /><br />Metal 2 pitch, μm                                      1.1

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

  • Application, features: Digital IC, highly-resistant,<br />Epitaxy =5 V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >7 V<br /><br />PMOS: Vtр=-0.6 V, Usd >7 V
  • Process Description: Number of photolithographies, pcs.              14<br /><br />Design rule, μm                                          0.35<br /><br />Substrate:                             725KDB0,015(100)<br /><br />Epitaxial layer:                                   15KDB12<br /><br />2 retrograde wells<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm              1.05 μm                                  <br /><br />Gate SiO2, Å                                             120<br /><br />Channel length<br /><br />NMOS/PMOS, μm                                     0.6<br /><br />N&amp;P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I                                     Ti/AlCu / Ti /TiN<br /><br />PolySi pitch, μm                                        1.0<br /><br />Contacts 1 (W-filled), μm                         ø 0.5<br /><br />Metal 1 pitch, μm                                    0.95<br /><br />Metal 2                                              Ti/AlCu<br /><br />Contacts 2 (W-filled), μm                       ø 0.5<br /><br />Metal 2 pitch, μm                                      1.2

Bipolar technology for the manufacture of positive and negative polarity voltage regulators, two metallization levels

  • Application, features: NPN Vertical:<br /><br />h 21E =(80-200)<br /><br />UCE >=18 V<br /><br />PNP Lateral:<br /><br />h 21E>=40<br /><br />UCE >=20V<br /><br />Capacitor: n+ - Al<br /><br />Resistors in layer:<br /><br />Base; resistor
  • Process Description: Number of masks, pcs.                                                                   11-13<br /><br />Mean design rule,µm                                                                            4-5<br /><br />Substrate:                           Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                                    Si/Sb-doped/ n-type/Thk5/Res17;<br /><br />                                                         Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                                      Si/P-doped/ n-type/Thk 10/ Res 1,25;<br /><br />Isolation:                                                                                   p-n junction<br /><br />Deep collector, separation and emitter layers have been carried out by method of diffusion.<br /><br />Base, resistor layers – by method of ion implantation<br /><br />Capacitor dielectric:                                                 Si oxide or Si nitride<br /><br />p-base depth, µm                                                                           1,8÷2,8<br /><br />N+emitter depth, µm                                                                      0,9÷2,2<br /><br />The first interlayer dielectric:        medium temperature PSG+ Si3N4<br /><br />The second interlayer dielectric:                        low temperature PSG<br /><br />The first  metallization level                                        AlSiCuTi  0,55 µm<br /><br />The second metallization level                                    AlSi, Al      1,4 µm<br /><br />Passivation:                                                         low temp. PSG   1,0 µm

90 V, p-n junction isolation, 1 PolySi, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors

  • Application, features: Small and medium-scale integration analogue IC, VDD <  90 V<br /><br />NPN Vertical:<br /><br />bn =50 Uсе=20 V<br /><br />PNP Lateral:<br /><br />bр =25 Uсе=20 V<br /><br />LNDMOS: Vtn= 2.0 V, Usd >90 V<br /><br />LPDMOS: Vtp= -1.4 V, Usd >90 V<br /><br />NMOS: Vtn= 1.2 V, Usd >18 V<br /><br />PMOS: Vtp= 1.5 V, Usd >18 V<br /><br />VNDMOS: Vtn= 2.0 V, Usd >70 V<br /><br /> <br /><br />Resistors in layer:<br /><br />NDMOS base, Р-drain, PolySi.<br /><br />Capacitors: PolySi-Si (SiO2 750Å)<br /><br />PolySi-Al (SiO2 8000 Å)
  • Process Description: Numberofmasks, pcs.                                             19<br /><br />Min design rule,µm                                              4.0<br /><br />Substrate:          Si/B-doped/  p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 20/Res 6;<br /><br />                                      Si/B-doped/ p-type/Thk 250/Res2.0 ;<br /><br />Epi layer:                     Si/P-doped/ n-type/ Thk 10/ Res 1.5;<br /><br />Isolation:                                                    p-n junction<br /><br />P-well depth, µm                                                     6.5<br /><br />NDMOS base depth, µm                                         2.5<br /><br />Gate SiO2, Å                                                          750<br /><br />NPN p-base depth, µm                                            2.5<br /><br />N+emitter depth, µm                                               0.5<br /><br />Interlayer dielectric - BPSG, µm                             0,8                                           <br /><br />Channel length (gate):<br /><br />N/PMOS, µm                                                         Ø 4<br /><br />Space line PolySi, µm                                                7<br /><br />Contacts, µm                                                              2<br /><br />Space line Me, µm                                                     8

1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate

  • Application, features: Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA<br /><br />PMOS: <br /><br />Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
  • Process Description: Number of masks, pcs.                                          9<br /><br />Design rules,µm                                            3,0-5,0<br /><br />Substrate:                    Si/P-doped/ n-type/Res 4.5<br /><br />P-well depth, µm                                                   6-8<br /><br />Gate SiO2, Å                                                          800<br /><br />Interlayer dielectric:                 medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm                       3<br /><br />Space line PolySi, µm                                           10<br /><br />Contacts , µm                                                            5<br /><br />Space line Me, µm                                                 12

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers

  • Application, features: IC for telephony,<br /><br />customized IC, VDD 3 V… 5  V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.6 V, Usd >10 V<br /><br />PMOS: <br /><br />Vtр=-0.7V, Usd >10 V
  • Process Description: Number of masks, pcs.                                 14 (16)<br /><br />Design rule,µm                                                 0.8<br /><br />Substrate: Si/P-doped/ n-type/Res 4.5<br /><br />or Si/B-doped/ p-type/Res 12;                      2 wells<br /><br />N/P-wells depth, µm                                           4/4<br /><br />Interlayer dielectric:                                       BPSG<br /><br />Gate SiO2, Å                                             130 /160<br /><br />Channel length NMOS/PMOS, µm               0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                               Ti-TiN/Al-Si/TiN<br /><br />Space line PolySi, µm                                         1.9<br /><br />Contacts 1, µm                                                Ø 0.9<br /><br />Space line Me 1   2.2Me 2                       Al-Si/TiN<br /><br />Contacts 2,µm                                                 Ø 0.9<br /><br />Space line Me 2, µm                                           2.4

1.5 V, 1.6 µm CMOS, 1 PolySi, 1 Me, low threshold, 150mm wafers

  • Application, features: Medium-scale integration digital IC for electronic timepieces and micro calculators, VDD 1.5 V¸3 V.<br /><br /> <br /><br />NMOS: Vtn= 0.5 V, Usd >10 V<br /><br />PMOS: Vtp= -0.5 V, Usd >10 V
  • Process Description: Number of masks, pcs.                                                    11<br /><br />Design rule,µm                                                              1.6<br /><br />Substrate:           Si/ B-doped/ p-type/Res 12          2 wells                          <br /><br />N/P-well depth, µm                                                        5/6<br /><br />Gate SiO2, Å                                                                 300<br /><br />Interlayer dielectric – BPSG<br /><br />Channel length: NMOS/PMOS, µm                               2.0<br /><br />space line PolySi , µm                                                    3.2    <br /><br />contacts, µm                                                                Ø 1.5<br /><br />space line Me, µm                                                           3.6   

15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

  • Application, features: Small and medium-scale integration logic IC, VDD < 20 V<br /><br /> <br /><br />NMOS: Vtn= 1.1 V, Usd >27 V<br /><br />PMOS: Vtp= -1.0 V, Usd >29 V
  • Process Description: Number of masks, pcs.                                           9<br /><br />Design rule,µm                                                    5.0<br /><br />Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100)                                                <br /><br />P-well depth, µm                                                   10<br /><br />Gate SiO2, Å                                                        950<br /><br />Interlayer dielectric:                    medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm                      5/6<br /><br />space line PolySi,µm                                            5.5<br /><br />contacts, µm                                                           Ø2<br /><br />space line  Me, µm                                                   8  

Bipolar technology for the manufacture of high-power npn-transistors with Darlington

  • Application, features: UCB = (300-350) V<br /><br />UCE = (150-350) V<br /><br /> Ic= (5-15) A<br /><br /> h21E >100
  • Process Description: Epi structure:<br /><br />Substrate:                         Si/ Sb-doped/ n-type/Res 0,01 (111):<br /><br />Thickness of Epi layer, µm                                                   27-38<br /><br />Resistivity, Ohm/cm                                                                  8-21<br /><br />6-7 masks (contact)<br /><br />Base: ion implantation,<br /><br />depth, µm                                                                                     6-8<br /><br />Emitter: diffusion,<br /><br />depth, µm                                                                              2,5-5,5<br /><br />collector-base p-n junction protection :                            SiPOS<br /><br />Metallization :                                                                   Al 4, 5 µm<br /><br />Backside:                                                                            Ti-Ni-Ag<br /><br />Passivation:                                                           Low temp. PSG

BiCDMOS 600 V, p-n junction isolation, 1 PolySi, 1 Me

  • Application, features: SMPS-IC  <br /><br />Low voltage NPN:<br /><br />h21E   50 min, Uсе 30V min<br /><br />PNP Lateral:<br /><br />h21E=2,2-30 Uсе=25-60 V<br /><br />NDMOS: Vtn=1.2-3.0 V,  Usd >=30 V<br /><br />Low voltage PMOS:<br /><br />Vtp=0.8-2.0 V, Usd  >=18 V<br /><br />High voltage PMOS:<br /><br />Vtp=0.8-2.0 V, Usd  >=22 V<br /><br />Low voltage NMOS:<br /><br />Vtn=0.8-2.0 V, Usd  >=18 V<br /><br />High voltage NMOS:<br /><br />Vtn=0.8-2.0 V, Usd  >=600 V
  • Process Description: Number of masks, pcs.                                              15<br /><br />Min design rule,µm                                                     3.0<br /><br />Substrate:           Si/B-doped/ p-type/ Thk 460/ Res 60/ (100)<br /><br />Isolation:                                                        p-n junction<br /><br />NDMOS base depth, µm                                             2.5<br /><br />Gate SiO2, Å                                                                 750<br /><br />Interlayer dielectric – medium temp. PSG, µm       0,8

BiCDMOS 48 V, p-n junction isolation, 1 PolySi, 1 Me

  • Application, features: Power electronics actuator  IC<br /><br />NPN Vertical:<br /><br />h21E=25-90 Uсе=20-70 V<br /><br />PNP Lateral:<br /><br />h21E=2,2-30 Uсе=25-60 V<br /><br />NDMOS: Vtn=1.8-2.6В, Usd=60-100 V<br /><br />Low voltage PMOS:<br /><br />Vtp=0.8-1.4 V, Usd =20-35 V<br /><br />High voltage PMOS:<br /><br />Vtp=1.2-2.2 V, Usd =30-80 V<br /><br />NMOS  transistor:<br /><br />Vtn=1.1-1.7 V, Usd =15-25 V
  • Process Description: Number of masks, pcs.                                               16<br /><br />Min design rule,µm                                                      3.0<br /><br />Substrate:            Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 20/Res 6;<br /><br />                                       Si/B-doped/ p-type/Thk 250/Res2.0<br /><br />Epi layer:                      Si/P-doped/ n-type/ Thk 12/ Res 1.5;<br /><br />Isolation:                                                         p-n junction<br /><br />P-well depth, µm                                                          5.0<br /><br />Gate SiO2, Å                                                                750<br /><br />Interlayer dielectric – Medium temp. PSG, µm       0,8

8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers

  • Application, features: Analogue-digital  IC for TV-receivers, Ucc=8V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >12 V<br /><br />PMOS: Vtр=-0.9 V, Usd >12 V<br /><br />NPN vertical:<br /><br />bn =120    Uce=10 V<br /><br />PNP lateral:<br /><br />bp =45      Uce=13 V
  • Process Description: Number of masks, pcs.                                           26<br /><br />Design rule,µm                                                     0.8<br /><br />Substrate:                           Si/B-doped/ p-type/Res 3<br /><br />Epitaxy:                 Si/P-doped/ n-type/ Thk 2.4/ Res 4.5<br /><br />p-well depth with p+cc, µm                                   4.3<br /><br />n-well depth with n+cc, µm                                   4.3<br /><br />Gate SiO2, Å                                                        130<br /><br />Interlayer dielectric:                                         BPSG<br /><br />Interlevel dielectric:                           PEoxide+ SOG<br /><br />NMOS/PMOS channel length, µm                 0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                               Ti-TiN/Al-Si/TiN<br /><br />Me II                                                      Ti/Al-Si/TiN<br /><br />NPN emitter size, µm                                    1.2*3.2<br /><br />Space line PolySi 2,µm                                       1.8<br /><br />Contacts 1, µm                                                  Ø 0.9<br /><br />Space line Me 1, µm                                             2.2<br /><br />Contacts 2,µm                                                  Ø 0.9<br /><br />Space line Me 2, µm                                             2.4

5 V, 3 µm CMOS, 1 PolySi, 1 Me

  • Application, features: Small and medium-scale integration logic IC, VDD < 5 V<br /><br /> <br /><br /> NMOS: <br /><br />Vtn=0.8-1.2 V, Ic >4 mA. Ubr>8V<br /><br />PMOS: <br /><br />Vtр=0.8-1.2 V, Ic >2 mA, Ubr>8V
  • Process Description: Number of masks, pcs.                                          11<br /><br />Design rule,µm                                                    2.0<br /><br />Substrate:                       Si/P-doped/ n-type/Res 4.5<br /><br />N/P-wells depth, µm                                            6-8<br /><br />Gate SiO2, Å                                              425 / 300<br /><br />Interlayer dielectric:                                        BPSG<br /><br />Channel length: NMOS/PMOS, µm                     3-4<br /><br />Space line PolySi, µm                                           10<br /><br />Contacts, µm                                                       4*4<br /><br />Space line Me, µm                                                10

Shottky diodes with Mo barrier

  • Application, features: Fast silicon Shottky diodes for switched mode power supplies <br /><br />Urev V   40-150<br /><br />Irev. µa   < 250<br /><br />Idirect max. A   1-30
  • Process Description: Number of masks, pcs.                                                  4<br /><br />Size, mm                                                  0.76x0.76-4x4<br /><br />Substrate: Si/As-doped/ n-type/Thk 460/Res 0.0035 (111)<br /><br />Epi layer:         Si/ P-doped/ n-type/Thk 4.5/Res (0.6-0.8)<br /><br />Isolation:                      p-n junction with field-type oxide<br /><br />Metallization:                                      Al+Mo+Ti-Ni-Ag

Bipolar technology for the manufacture of high-power npn-transistors with Darlington

  • Application, features: UCB = (60-70) V<br /><br />UCE = (60-70) V<br /><br /> Ic= (2,0-12) A<br /><br /> h21E >500
  • Process Description: Epi structure:<br /><br />Substrate:                        Si/ B-doped/ p-type/ Res 0,05/ (111):<br /><br />Thickness of the layer, µm                                                 25-33<br /><br />Resistivity, Ohm/cm                                                            10-18<br /><br />6,7 masks (contact)<br /><br />Base: Phosphorous ion implantation,<br /><br />depth, µm                                                                                   6-8<br /><br />Emitter: boron diffusion,<br /><br />depth, µm                                                                            2,5-5,5<br /><br />p-n junction protection :                                          SiO2, Ta2O5<br /><br />Metallization :                                                                  Al 4, 5 µm<br /><br />Backside:                                                                            Ti-Ni-Ag

Bipolar technology for the manufacture of high-power npn-transistors with the range of operating voltages: 300-700 V

  • Application, features: UCB = (300-700) V<br /><br />UCE = (300-400) V<br /><br /> Ic= (0,5-8,0) A<br /><br /> h21E =(8-40)
  • Process Description: Epi structure<br /><br />Substrate:                        Si/ Sb-doped/ n-type/Res 0,01 (111):<br /><br />Thickness of Epi layer, µm                                                 50-80<br /><br />Resistivity, Ohm/cm                                                             40-50<br /><br />7-8 masks (contact)<br /><br />Base: ion implantation,<br /><br />depth, µm                                                                             2,8-4,6<br /><br />Emitter: diffusion,<br /><br />depth, µm                                                                             1,4-2,8<br /><br />collector-base p-n junction protection:                            SiPOS<br /><br />Metallization :                                                       Al   1,4 ; 4, 5 µm<br /><br />Backside:                                                                           Ti-Ni-Ag<br /><br />Passivation:                                                         Low temp. PSG

Bipolar technology for the manufacture of voltage regulators of positive and negative polarity, one metallization level

  • Application, features: NPN  Vertical:<br /><br />h 21E =(100-300)<br /><br />UCE >=38V<br /><br />PNP Lateral:<br /><br />h 21E>=20<br /><br />UCE >=38V<br /><br />Capacitor: n+ - Al<br /><br />Resistors in layer:<br /><br />Base; resistor
  • Process Description: Number of masks, pcs.                                                            7-10<br /><br />Mean design rule,µm                                                                  4-5<br /><br />Substrate:                 Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                           Si/Sb-doped/ n-type/Thk5/Res25;<br /><br />                                       Si/Boron-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                            Si/P-doped/ n-type/Thk 13,3/ Res 3.6;<br /><br />Isolation:                                                                          p-n junction<br /><br />p-base depth, µm                                                                  1,8÷2,8<br /><br />N+emitter depth, µm                                                             0,9÷2,2<br /><br />Deep collector, separation and emitter layers have been carried out by method of diffusion<br /><br />Capacitor dielectric:                                        Si oxide or Si nitride<br /><br />Interlayer dielectric:                              medium temperature PSG<br /><br />Metallization:                                                                      Al   1,4 µm<br /><br />Passivation:                                                 low temp. PSG 1,0 µm

40 V, p-n junction isolation “Bp30-40”

  • Application, features: Small-scaleintegrationdigital-analogueIC, VDD< 40 V<br /><br /> <br /><br />NPNtransistor vertical:<br /><br />bn =150 Uce=48 V<br /><br />РNP transistor lateral:<br /><br />bр =65 Uсе=60 V<br /><br />РNP transistorvertical:<br /><br />bр =60 Uсе=60 V<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor.<br /><br />PolySi
  • Process Description: Number of masks, pcs.                                                       8-13<br /><br />Mean design rule,µm                                                              8.0<br /><br />Substrate:            Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                Si/Sb-doped/ n-type/Thk 6.0/Res20;<br /><br />                                    Si/B-doped/ p-type/Thk 1.95/Res210 ;<br /><br />Epi layer:                       Si/P-doped/ n-type/Thk 13/ Res 3.5;<br /><br />Isolation:                                                    p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      9*9<br /><br />Distance between transistors, mm                                        4<br /><br />Switching:<br /><br />contacts 1, µm                                                                         3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts 2, µm                                                                        4*4<br /><br />space line Me 2, µm                                                            14.0

20 V,p-n junction isolation “Bp30С-20” complementary

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor  vertical:<br /><br />bn=150 Uce=27 V<br /><br />РNP transistor  lateral:<br /><br />bр=30 Uсе=35 V<br /><br />РNP transistor  vertical:<br /><br />bр=45 Uсе=35 V<br /><br />РNP Vertical with isolated collector:<br /><br />bр=80 Uсе=30 V<br /><br />Capacitors:emitter-base; collector base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                     12-14<br /><br />Mean design rule,µm                                                              6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/  (111)<br /><br />Buried layers:                Si/Sb-doped/n-type/Thk 6.0/Res  20;<br /><br />                                    Si/ B-doped/p-type/Thk 1.95/Res    210;<br /><br />Epi layer:                       Si/P-doped/ n-type/ Thk 8/ Res     1.5;<br /><br />Isolation:                                                   p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      7*7<br /><br />Distance between transistors, µm                                         4<br /><br />Switching: <br /><br />contacts 1, µm                                                                        3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line  Me 2, µm                                                           12.0

0 V, p-n junction isolation “Bp30-20”

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP transistor lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP transistor  vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                  8-13<br /><br />Mean design rule,µm                                                        6.0<br /><br />Substrate:      Si/B-doped/ p-type/ Thk 460/ Res 10/  (111)<br /><br />Buried layers:           Si/ Sb-doped/ n-type/Thk 6.0/Res 20;<br /><br />                                 Si/ B-doped /p-type/Thk 1.95/Res210;<br /><br />Epi layer:                     Si/ P-doped/ n-type/ Thk 9/ Res 2.0;<br /><br />Isolation:                                                 p-n junction<br /><br />p-base depth, µm                                                              2.2<br /><br />N+emitter depth, µm                                                         1.7<br /><br />Emitter size, µm                                                                9*9<br /><br />Distance between transistors, µm                                    4<br /><br />Switching:  <br /><br />contacts 1, µm                                                                   3*3<br /><br />space line  Me 1, µm                                                         9.0<br /><br />contacts  2, µm                                                                  4*4<br /><br />space line Me 2, µm                                                       12.0

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

  • Application, features: MOSFET<br /><br />NMOS: Vtn=2÷4 V<br /><br />Umax= 60÷900 V
  • Process Description: Number of masks, pcs.                                                8<br /><br />Min design rule,µm                                                    2.0<br /><br />Substrate:                  Si/Sb-doped/ n-type/Res 0,015; <br /><br />                                   Si/ As-doped/ n-type/ Res 0,003<br /><br />Epi layer:<br /><br />thickness                                                         8÷75) µm<br /><br />Resistivity                                     (0,67÷31,5) Ohm/cm<br /><br />Gate oxide                                                  (60÷100) nm<br /><br />Interlayer dielectric       medium temp. oxide + BPSG <br /><br />Passivation                                    PEoxide + PE SI3N4

1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link

  • Application, features: CMOS master-slice chip<br /><br /> NMOS: <br /><br />Vtn=1.0 V, Ic >10 mA. Ubr>12V<br /><br /> <br /><br />PMOS: <br /><br />Vtр=1.0 V, Ic >4.0 mA, Ubr>12V
  • Process Description: Number of masks, pcs.                                              11<br /><br />Design rule,µm                                                        1.2<br /><br />Substrate:                            Si/B-doped / p-type/Res 12<br /><br />N/P-well depth, µm                                                  5/6<br /><br />Gate SiO2, Å                                                    250-300<br /><br />Interlayer dielectric:                                            BPSG<br /><br />Channel length: NMOS/PMOS, µm                         2.0<br /><br />Contacts, µm                                                     2.0x2.0<br /><br />Space line Me1, µm                                                    8<br /><br />Space line Me 2, µm                                                  10