20 V, p-n junction isolation

20 V, p-n junction isolation

20 V, p-n junction isolation
  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                         13<br /><br />Mean design rule,µm                                                            6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 5/Res 17;<br /><br />                                        Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                    Si/P-doped/ N-type/ Thk 10/ Res 1.25;<br /><br />Isolation:                                                                  p-n junction<br /><br />p-base depth, µm                                                                   2.4<br /><br />N+emitter depth, µm                                                              1.7<br /><br />Emitter size, µm                                                                         6<br /><br />Distance between transistors, µm                                         6<br /><br />Switching: <br /><br />contacts 1, µm                                                                            4<br /><br />space line  Me 1, µm                                                           13.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line Me 2, µm                                                             12.0
  • Тип карточки товара: Сложная
  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                         13<br /><br />Mean design rule,µm                                                            6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 5/Res 17;<br /><br />                                        Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                    Si/P-doped/ N-type/ Thk 10/ Res 1.25;<br /><br />Isolation:                                                                  p-n junction<br /><br />p-base depth, µm                                                                   2.4<br /><br />N+emitter depth, µm                                                              1.7<br /><br />Emitter size, µm                                                                         6<br /><br />Distance between transistors, µm                                         6<br /><br />Switching: <br /><br />contacts 1, µm                                                                            4<br /><br />space line  Me 1, µm                                                           13.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line Me 2, µm                                                             12.0