3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers

規格
購買和技術。支持

範圍	意義
Тип карточки товара	Сложная
Application, features	IC for telephony, customized IC, VDD 3 V… 5 V NMOS: Vtn=0.6 V, Usd >10 V PMOS: Vtр=-0.7 V, Usd >10 V
Process Description	Number of masks, pcs. 14 (16) Design rule,µm 0.8 Substrate: Si/ P-doped/n-type/Res 4.5 or Si/B-doped/ p-type/Res 12; 2 wells N/P-wells depth, µm 4/4 Interlayer dielectric: SACVD SiO2 + PE (TEOS) 1,05 µm Gate SiO2, Å 130/160 NMOS/PMOS channel length, µm 0.9/1.0 N&P LDD- drains Me I Ti/AlCu/Ti/TiN Space line PolySi,µm 1.9 Contacts 1 (filled in by W), µm Ø 0.7 Space line Me 1, µm 2.2 Me2 Ti/AlCu Contacts 2 (filled in by W),µm Ø 0.7 Space line Me 2, µm 2.4

訂購

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