1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate

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範圍	意義
Тип карточки товара	Сложная
Application, features	Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V NMOS: Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA PMOS: Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
Process Description	Number of masks, pcs. 9 Design rules,µm 3,0-5,0 Substrate: Si/P-doped/ n-type/Res 4.5 P-well depth, µm 6-8 Gate SiO2, Å 800 Interlayer dielectric: medium temp. PSG Channel length: NMOS/PMOS, µm 3 Space line PolySi, µm 10 Contacts , µm 5 Space line Me, µm 12

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