雙擴散金屬氧化物半導體工藝

	指定	The prototype	Av (V/mV) Min	Battery Current, IBAT1 (max), nA	Battery Supply Voltage, VBAT	External Caps (mF)	Features	Application, features	Process Description	Frequency, kHz	FT, МHz	Functions: 12H/24H	Ucc ЖКИ,В	Uds, В	Ui max, В	Uo, В	Uref, В, (max)	Uref, В, (min)	U меж.баз., В (max)
	Field P DMOS transistors	UT54ACS164245	4	4	4	4	3		Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/Res 0,005 Epi layer: thickness (15-34) µm Resistivity (2÷21) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric medium temp. PSG Passivation: low temp. PSG	2	1	1	23423	4324	324	32423	423	423	324
Field P DMOS transistors 技術。支持
	Field N DMOS transistors							MOSFET Low-power Vtn= 0,6-3,0V Ubr=50-200V Pmax=1,0 Watt High-power Vtn= 2,0-4,0V Ubr=50-600V Pmax=200 Watt	Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/Sb-doped/ n-type/Res 0,01 Epi layer: Thickness (9÷42) µm Resistivity (0,7÷16) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric - medium temp. PSG Passivation: low temp. PSG
Field N DMOS transistors 技術。支持
	Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers							MOSFET NMOS: Vtn=2÷4 V Umax= 60÷900 V	Number of masks, pcs. 8 Min design rule,µm 2.0 Substrate: Si/Sb-doped/ n-type/Res 0,015; Si/ As-doped/ n-type/ Res 0,003 Epi layer: thickness 8÷75) µm Resistivity (0,67÷31,5) Ohm/cm Gate oxide (60÷100) nm Interlayer dielectric medium temp. oxide + BPSG Passivation PEoxide + PE SI3N4
Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers 技術。支持