5 V, 1.2 µm CMOS, 2 PolySi, 2 Me, low voltage EEPROM, 150 mm wafers

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範圍	意義
Тип карточки товара	Сложная
Application, features	LSI EEPROM, VDD:2,4 V… 6 V LV NMOS: Vtn=(0.4-0,8)V, Usd>=12 V LV PMOS: Vtр=-(0.5-0,9)V, Usd ≤-12 V HV- NMOS: Vtn=(0,3-0,6)V, Usd>=17 V HV- РMOS: Vtр=-(0,6-1,0)V, Usd ≤-15 V
Process Description	Number of masks, pcs. 3 (marked) Design rule, µm 1.2 Substrate: Si/B-doped/ p-type/Res 12, 2 wells N/P-well depth, µm 5/6 Gate SiO2: Low voltage transistors, Å 250 High voltage transistors, Å 350 Tunnel SiO2, Å 77 Interlayer dielectric-1: Si3N4, Å 350 Interlayer dielectric -2: BPSG, Å 7000 Interlevel dielectric: PEoxide+SOG+ PEoxide Channel length: Low voltage NMOS/PMOS, µm 1.4/1.6 High voltage NMOS/PMOS, µm 2.6/2.6 N & P LDD- drains Built-in transistors Space line PolySi 1, µm 3.2 Space line PolySi 2, contact free, µm 2.4 Space line PolySi 2, with contact, µm 4,6 Contacts-1, µm Ø 1.2 Space line Me 1, contact free, µm 3.2 Space line Me 2, with contact, µm 4,4 Contacts 2, µm Ø 1.4 Space line Me 2, contact free, µm 4.4 Space line Me 2, with contact, µm 4,8

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