5 V, 1.5 µm CMOS, 1 PolySi, 2 Me

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範圍	意義
Тип карточки товара	Сложная
Application, features	Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn= 0.8 V, Usd >12 V PMOS: Vtp= -0.8 V, Usd >12 V
Process Description	Number of masks, pcs. 14 Design rule,µm 1.5 Substrate: Si/ P-doped/n-type/Res 4.5 N/P-well depth, µm 5/5 Interlayer dielectric: BPSG Interlevel dielectric: PE oxide Gate SiO2, Å 245 Channel length: NMOS/PMOS,µm 1.4/2.0 N LDD-drains space line PolySi , µm 3.4 contacts 1, µm 1.54.5 space line Me 1, µm 6.0 contacts 2, µm 3.04.5 space line Me 2, µm 9.5

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