互补金属氧化物半导体流程

	指定	Application, features	Process Description
	CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer	Digital IC, Epitaxy =2.4¸6.0 V For 3.0 V NMOS: Vtn=0.6 V, Usd >5 V PMOS: Vtр=-0.6 V, Usd >5 V For 5.0 V NMOS: Vtn=1.0 V, Usd >8 V PMOS: Vtр=-0.9 V, Usd >8 V	Number of photolithographies, pcs. 22 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 retrograde wells for high-voltage transistors 2 retrograde wells for low-voltage transistors Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 70 for low-voltage transistors 350 for high-voltage transistors Channel length NMOS/PMOS, μm 0.35 for low-voltage transistors NMOS/PMOS, μm 1.0 for high-voltage transistors N&P LDD- drains Titanium silicide Metal I,2 Ti/AlCu / Ti /TiN Contacts 1 (W-filled), μm ø 0.4 Metal 1 pitch, μm 0.95 Metal Ti/AlCu Contacts 2,3 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1
CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer 技術。支持
	3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers	IC for telephony, customized IC, VDD 3 V… 5 V NMOS: Vtn=0.6 V, Usd >10 V PMOS: Vtр=-0.7 V, Usd >10 V	Number of masks, pcs. 14 (16) Design rule,µm 0.8 Substrate: Si/ P-doped/n-type/Res 4.5 or Si/B-doped/ p-type/Res 12; 2 wells N/P-wells depth, µm 4/4 Interlayer dielectric: SACVD SiO2 + PE (TEOS) 1,05 µm Gate SiO2, Å 130/160 NMOS/PMOS channel length, µm 0.9/1.0 N&P LDD- drains Me I Ti/AlCu/Ti/TiN Space line PolySi,µm 1.9 Contacts 1 (filled in by W), µm Ø 0.7 Space line Me 1, µm 2.2 Me2 Ti/AlCu Contacts 2 (filled in by W),µm Ø 0.7 Space line Me 2, µm 2.4
3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers 技術。支持
	5 V, 1.2 µm CMOS, 2 PolySi, 2 Me, low voltage EEPROM, 150 mm wafers	LSI EEPROM, VDD:2,4 V… 6 V LV NMOS: Vtn=(0.4-0,8)V, Usd>=12 V LV PMOS: Vtр=-(0.5-0,9)V, Usd ≤-12 V HV- NMOS: Vtn=(0,3-0,6)V, Usd>=17 V HV- РMOS: Vtр=-(0,6-1,0)V, Usd ≤-15 V	Number of masks, pcs. 3 (marked) Design rule, µm 1.2 Substrate: Si/B-doped/ p-type/Res 12, 2 wells N/P-well depth, µm 5/6 Gate SiO2: Low voltage transistors, Å 250 High voltage transistors, Å 350 Tunnel SiO2, Å 77 Interlayer dielectric-1: Si3N4, Å 350 Interlayer dielectric -2: BPSG, Å 7000 Interlevel dielectric: PEoxide+SOG+ PEoxide Channel length: Low voltage NMOS/PMOS, µm 1.4/1.6 High voltage NMOS/PMOS, µm 2.6/2.6 N & P LDD- drains Built-in transistors Space line PolySi 1, µm 3.2 Space line PolySi 2, contact free, µm 2.4 Space line PolySi 2, with contact, µm 4,6 Contacts-1, µm Ø 1.2 Space line Me 1, contact free, µm 3.2 Space line Me 2, with contact, µm 4,4 Contacts 2, µm Ø 1.4 Space line Me 2, contact free, µm 4.4 Space line Me 2, with contact, µm 4,8
5 V, 1.2 µm CMOS, 2 PolySi, 2 Me, low voltage EEPROM, 150 mm wafers 技術。支持
	5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers	Medium-scale integration EEPROM, VDD:2,4 V… 6 V NMOS: Vtn=(0,65+-0,25)V, Usd >=12 V PMOS: Vtр=-(0,8+-0,2)V, Usd ≤-12 V HV- NMOS: Vtn=(0,45+0,15)V Usd³17 V HV- РMOS: Vtр=-(0,8+0,2)V Usd ≤-16 V	Number of masks, pcs. 17 Design rule, µm 1.6 Substrate: Si/B-doped/p-type/Res 12 2 wells N/P-well depth, µm 5/6 Gate SiO2, Å 425 Tunnel SiO2, Å 77 Interlayer dielectric-1: Si3N4, Å 350 Interlayer dielectric -2: BPSG, Å 7000 Built-in transistors Channel length: NMOS/PMOS Low-voltage transistors, µm 2.4 High- voltage transistors, µm 3.6 Space line PolySi 1, µm 3.2 Space line PolySi 2, µm 4.2 Contacts, mm Ø 1.2 Space line Me, µm 4.4
5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers 技術。支持
	CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer	Digital IC, highly-resistant, Epitaxy = 3 V NMOS: Vtn=0.6 V, Usd >5 V PMOS: Vtр=-0.6 V, Usd >5 V	Number of photolithographies, pcs. 15 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 retrograde wells Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 70 Channel length NMOS/PMOS, μm 0.35 N&P LDD- drains Titanium silicide Metal I Ti/AlCu / Ti /TiN PolySi pitch, μm 0.8 Contacts 1 (W-filled), μm ø 0.5 Metal 1 pitch, μm 0.95 Metal 2 Ti/AlCu Contacts 2 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1
CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer 技術。支持
	1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate	Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V NMOS: Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA PMOS: Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA	Number of masks, pcs. 9 Design rules,µm 3,0-5,0 Substrate: Si/P-doped/ n-type/Res 4.5 P-well depth, µm 6-8 Gate SiO2, Å 800 Interlayer dielectric: medium temp. PSG Channel length: NMOS/PMOS, µm 3 Space line PolySi, µm 10 Contacts , µm 5 Space line Me, µm 12
1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate 技術。支持
	3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers	IC for telephony, customized IC, VDD 3 V… 5 V NMOS: Vtn=0.6 V, Usd >10 V PMOS: Vtр=-0.7V, Usd >10 V	Number of masks, pcs. 14 (16) Design rule,µm 0.8 Substrate: Si/P-doped/ n-type/Res 4.5 or Si/B-doped/ p-type/Res 12; 2 wells N/P-wells depth, µm 4/4 Interlayer dielectric: BPSG Gate SiO2, Å 130 /160 Channel length NMOS/PMOS, µm 0.9/1.0 N&P LDD- drains Me I Ti-TiN/Al-Si/TiN Space line PolySi, µm 1.9 Contacts 1, µm Ø 0.9 Space line Me 1 2.2Me 2 Al-Si/TiN Contacts 2,µm Ø 0.9 Space line Me 2, µm 2.4
3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers 技術。支持
	5 V, 1.5 µm CMOS, 1 PolySi, 1 Ме, PolySi- resistors, 150mm wafers	Supply voltage controllers NMOS: Vtn= 0.5 V, Usd >10 V PMOS: Vtp= 0.5V, Usd >10 V	Number of masks, pcs. 17 Design rule,µm 1.5 Substrate: Si/B-doped/p-type/Res 12; 2 wells N/P-well depth, µm 5/6 P-type PolySi resistors Bipolar vertical NPN transistor Gate SiO2, Å 250 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 1.7 N&P LDD- drains Space line PolySi, µm 2.5 Contacts, µm Ø 1.3 Space line Me, µm 3.5
5 V, 1.5 µm CMOS, 1 PolySi, 1 Ме, PolySi- resistors, 150mm wafers 技術。支持
	1.5 V, 1.6 µm CMOS, 1 PolySi, 1 Me, low threshold, 150mm wafers	Medium-scale integration digital IC for electronic timepieces and micro calculators, VDD 1.5 V¸3 V. NMOS: Vtn= 0.5 V, Usd >10 V PMOS: Vtp= -0.5 V, Usd >10 V	Number of masks, pcs. 11 Design rule,µm 1.6 Substrate: Si/ B-doped/ p-type/Res 12 2 wells N/P-well depth, µm 5/6 Gate SiO2, Å 300 Interlayer dielectric – BPSG Channel length: NMOS/PMOS, µm 2.0 space line PolySi , µm 3.2 contacts, µm Ø 1.5 space line Me, µm 3.6
1.5 V, 1.6 µm CMOS, 1 PolySi, 1 Me, low threshold, 150mm wafers 技術。支持
	CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer	Digital IC with EEPROM, Epitaxy =2.4¸6.0 V For low-voltage transistors NMOS: Vtn=0.5 V, Usd >7 V PMOS: Vtр=-0.6 V, Usd >7 V For high-voltage transistors Vtn=0.6 V, Usd >16 V PMOS: Vtр=-0.6 V, Usd >9 V	Number of photolithographies, pcs. 27 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 wells Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 250 Tunnel oxide, Å 75 Capacitor dielectric Si3N4, Å 250 Channel length NMOS/PMOS, μm 0.35 for low-voltage transistors NMOS/PMOS, μm 2.5/1.0 for high-voltage transistors N&P LDD- drains Titanium silicide Metal I,2 Ti/AlCu / Ti /TiN Contacts 1 (W-filled) ø 0.5 Metal 1 pitch, μm 0.95 Metal 3 Ti/AlCu Contacts 2,3 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1
CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer 技術。支持
	5 V, 2 µm CMOS, 1 PolySi, 1 Me	Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn=0.6/ 0.5 V, Usd >12 V PMOS: Vtр=-0,7V/-0,5, Usd >14 V	Number of masks, pcs. 11 Design rule, µm 2.0 Substrate: Si/ /n -type/ Phosphorus/Res 4.5, 2 wells N/P-well depth, µm 6/7 Gate SiO2, Å 425/300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 2.5 Space line PolySi, µm 4.5 Contacts, µm 2.4*2.4 Space line Me, µm 8.5
5 V, 2 µm CMOS, 1 PolySi, 1 Me 技術。支持
	15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate	Small and medium-scale integration logic IC, VDD < 20 V NMOS: Vtn= 1.1 V, Usd >27 V PMOS: Vtp= -1.0 V, Usd >29 V	Number of masks, pcs. 9 Design rule,µm 5.0 Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100) P-well depth, µm 10 Gate SiO2, Å 950 Interlayer dielectric: medium temp. PSG Channel length: NMOS/PMOS, µm 5/6 space line PolySi,µm 5.5 contacts, µm Ø2 space line Me, µm 8
15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate 技術。支持
	CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer	Digital IC, highly-resistant, Epitaxy =5 V NMOS: Vtn=0.6 V, Usd >7 V PMOS: Vtр=-0.6 V, Usd >7 V	Number of photolithographies, pcs. 14 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 retrograde wells Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 120 Channel length NMOS/PMOS, μm 0.6 N&P LDD- drains Titanium silicide Metal I Ti/AlCu / Ti /TiN PolySi pitch, μm 1.0 Contacts 1 (W-filled), μm ø 0.5 Metal 1 pitch, μm 0.95 Metal 2 Ti/AlCu Contacts 2 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.2
CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer 技術。支持
	1.2 µm CMOS, 1 PolySi, 2 Me	CMOS master-slice chip NMOS: Vtn=0.7 V, Ic >11.5 mA. Ubr>12V PMOS: Vtр=0.8 V, Ic >4.5 mA, Ubr>12V	Number of masks, pcs. 11 Design rules,µm 1.2 Substrate: Si/B-doped/ p-type/Res 12 N/P-wells depth, µm 5/6 Gate SiO2, Å 250-300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 1.4/1.6 Space line PolySi, µm 2.8 Contacts, µm 1.6x1.6 Space line Me1, µm 3.4 Space line Me2, µm 3
1.2 µm CMOS, 1 PolySi, 2 Me 技術。支持
	5 V, 3 µm CMOS, 1 PolySi, 1 Me	Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn=0.8-1.2 V, Ic >4 mA. Ubr>8V PMOS: Vtр=0.8-1.2 V, Ic >2 mA, Ubr>8V	Number of masks, pcs. 11 Design rule,µm 2.0 Substrate: Si/P-doped/ n-type/Res 4.5 N/P-wells depth, µm 6-8 Gate SiO2, Å 425 / 300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 3-4 Space line PolySi, µm 10 Contacts, µm 4*4 Space line Me, µm 10
5 V, 3 µm CMOS, 1 PolySi, 1 Me 技術。支持
	5 V, 1.5 µm CMOS, 1 PolySi, 2 Me	Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn= 0.8 V, Usd >12 V PMOS: Vtp= -0.8 V, Usd >12 V	Number of masks, pcs. 14 Design rule,µm 1.5 Substrate: Si/ P-doped/n-type/Res 4.5 N/P-well depth, µm 5/5 Interlayer dielectric: BPSG Interlevel dielectric: PE oxide Gate SiO2, Å 245 Channel length: NMOS/PMOS,µm 1.4/2.0 N LDD-drains space line PolySi , µm 3.4 contacts 1, µm 1.54.5 space line Me 1, µm 6.0 contacts 2, µm 3.04.5 space line Me 2, µm 9.5
5 V, 1.5 µm CMOS, 1 PolySi, 2 Me 技術。支持
	5 V, 1.5 µm CMOS, 1 PolySi, 1 Me, 150mm wafers	Digital IMC, microcontrollers with VDD= 5V NMOS: Vtn= 0.6V, Usd >10 V PMOS: Vtp= 1.0V, Usd >13 V	Number of masks, pcs. 16 Design rule,µm 1.5 Substrate: Si/B-doped/ p-type/Res 12 2 wells N/P-well depth, µm 5/6 Interlayer dielectric: BPSG Gate SiO2, Å 250 Interlayer dielectric: BPSG Transistor built in ROM Buried contacts Channel length: NMOS/PMOS, µm 1.5 N & P LDD- drains space line PolySi,µm 2.5 contacts, µm Ø 1.5 space line Me,µm 3.5
5 V, 1.5 µm CMOS, 1 PolySi, 1 Me, 150mm wafers 技術。支持
	1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link	CMOS master-slice chip NMOS: Vtn=1.0 V, Ic >10 mA. Ubr>12V PMOS: Vtр=1.0 V, Ic >4.0 mA, Ubr>12V	Number of masks, pcs. 11 Design rule,µm 1.2 Substrate: Si/B-doped / p-type/Res 12 N/P-well depth, µm 5/6 Gate SiO2, Å 250-300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 2.0 Contacts, µm 2.0x2.0 Space line Me1, µm 8 Space line Me 2, µm 10
1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link 技術。支持