CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer

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範圍	意義
Тип карточки товара	Сложная
Application, features	Digital IC, Epitaxy =2.4¸6.0 V For 3.0 V NMOS: Vtn=0.6 V, Usd >5 V PMOS: Vtр=-0.6 V, Usd >5 V For 5.0 V NMOS: Vtn=1.0 V, Usd >8 V PMOS: Vtр=-0.9 V, Usd >8 V
Process Description	Number of photolithographies, pcs. 22 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 retrograde wells for high-voltage transistors 2 retrograde wells for low-voltage transistors Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 70 for low-voltage transistors 350 for high-voltage transistors Channel length NMOS/PMOS, μm 0.35 for low-voltage transistors NMOS/PMOS, μm 1.0 for high-voltage transistors N&P LDD- drains Titanium silicide Metal I,2 Ti/AlCu / Ti /TiN Contacts 1 (W-filled), μm ø 0.4 Metal 1 pitch, μm 0.95 Metal Ti/AlCu Contacts 2,3 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1

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