双极流程

Bipolar technology for the manufacture of high-power npn-transistors with operating voltage of 1500 V

Application, features: UCE = 1500 V UCE = (700-800) V Ic= (5-12) A
Process Description: Substrate: Si/ P-irradiated /Res 102- 90 8 masks (contact): Base: ion implantation depth, µm 20-26 Emitter : diffusion, depth, µm 10-15 collector-base p-n junction protection : SiPOS Metallization : Al 4, 5 µm Radiation treatment to ensure dynamics Backside matting Backside: Ti-Ni-Ag sputtering

Bipolar technology for the manufacture of positive and negative polarity voltage regulators, two metallization levels

Application, features: NPN Vertical: h 21E =(80-200) UCE >=18 V PNP Lateral: h 21E>=40 UCE >=20V Capacitor: n+ - Al Resistors in layer: Base; resistor
Process Description: Number of masks, pcs. 11-13 Mean design rule,µm 4-5 Substrate: Si/B-doped/ p-type/Thk 460/Res 10/ (111) Buried layers: Si/Sb-doped/ n-type/Thk5/Res17; Si/B-doped/ p-type/Thk 1.6/Res510; Epi layer: Si/P-doped/ n-type/Thk 10/ Res 1,25; Isolation: p-n junction Deep collector, separation and emitter layers have been carried out by method of diffusion. Base, resistor layers – by method of ion implantation Capacitor dielectric: Si oxide or Si nitride p-base depth, µm 1,8÷2,8 N+emitter depth, µm 0,9÷2,2 The first interlayer dielectric: medium temperature PSG+ Si3N4 The second interlayer dielectric: low temperature PSG The first metallization level AlSiCuTi 0,55 µm The second metallization level AlSi, Al 1,4 µm Passivation: low temp. PSG 1,0 µm

Bipolar technology for the manufacture of high-power npn-transistors with Darlington

Application, features: UCB = (300-350) V UCE = (150-350) V Ic= (5-15) A h21E >100
Process Description: Epi structure: Substrate: Si/ Sb-doped/ n-type/Res 0,01 (111): Thickness of Epi layer, µm 27-38 Resistivity, Ohm/cm 8-21 6-7 masks (contact) Base: ion implantation, depth, µm 6-8 Emitter: diffusion, depth, µm 2,5-5,5 collector-base p-n junction protection : SiPOS Metallization : Al 4, 5 µm Backside: Ti-Ni-Ag Passivation: Low temp. PSG

Bipolar technology for the manufacture of high-power npn-transistors with the range of operating voltages: 300-700 V

Application, features: UCB = (300-700) V UCE = (300-400) V Ic= (0,5-8,0) A h21E =(8-40)
Process Description: Epi structure Substrate: Si/ Sb-doped/ n-type/Res 0,01 (111): Thickness of Epi layer, µm 50-80 Resistivity, Ohm/cm 40-50 7-8 masks (contact) Base: ion implantation, depth, µm 2,8-4,6 Emitter: diffusion, depth, µm 1,4-2,8 collector-base p-n junction protection: SiPOS Metallization : Al 1,4 ; 4, 5 µm Backside: Ti-Ni-Ag Passivation: Low temp. PSG

Shottky diodes with Mo barrier

Application, features: Fast silicon Shottky diodes for switched mode power supplies Urev V 40-150 Irev. µa < 250 Idirect max. A 1-30
Process Description: Number of masks, pcs. 4 Size, mm 0.76x0.76-4x4 Substrate: Si/As-doped/ n-type/Thk 460/Res 0.0035 (111) Epi layer: Si/ P-doped/ n-type/Thk 4.5/Res (0.6-0.8) Isolation: p-n junction with field-type oxide Metallization: Al+Mo+Ti-Ni-Ag

Bipolar technology for the manufacture of high-power npn-transistors with Darlington

Application, features: UCB = (60-70) V UCE = (60-70) V Ic= (2,0-12) A h21E >500
Process Description: Epi structure: Substrate: Si/ B-doped/ p-type/ Res 0,05/ (111): Thickness of the layer, µm 25-33 Resistivity, Ohm/cm 10-18 6,7 masks (contact) Base: Phosphorous ion implantation, depth, µm 6-8 Emitter: boron diffusion, depth, µm 2,5-5,5 p-n junction protection : SiO2, Ta2O5 Metallization : Al 4, 5 µm Backside: Ti-Ni-Ag

Bipolar technology for the manufacture of npn-transistors with the range of collector current: 7,5÷16 A

Application, features: UCB = (80-160) V UCE = (30-90) V Ic= (7,5-16) A h21E >15
Process Description: Epi structure Substrate: Si/B-doped/ p-type/ Res 0,05/ (111): Thickness of Epi layer, µm 25-28 Resistivity, Ohm/cm 8-11 7 masks (contact) Base:Phosphorous ion implantation, depth, µm 4,5-7,5 Emitter: boron diffusion, depth, µm 1,4-2,5 p-n junction protection : SiO2, Ta2,O5 Metallization : Al 4, 0 µm Backside: Ti-Ni-Ag

Bipolar technology for the manufacture of voltage regulators of positive and negative polarity, one metallization level

Application, features: NPN Vertical: h 21E =(100-300) UCE >=38V PNP Lateral: h 21E>=20 UCE >=38V Capacitor: n+ - Al Resistors in layer: Base; resistor
Process Description: Number of masks, pcs. 7-10 Mean design rule,µm 4-5 Substrate: Si/B-doped/ p-type/Thk 460/Res 10/ (111) Buried layers: Si/Sb-doped/ n-type/Thk5/Res25; Si/Boron-doped/ p-type/Thk 1.6/Res510; Epi layer: Si/P-doped/ n-type/Thk 13,3/ Res 3.6; Isolation: p-n junction p-base depth, µm 1,8÷2,8 N+emitter depth, µm 0,9÷2,2 Deep collector, separation and emitter layers have been carried out by method of diffusion Capacitor dielectric: Si oxide or Si nitride Interlayer dielectric: medium temperature PSG Metallization: Al 1,4 µm Passivation: low temp. PSG 1,0 µm

40 V, p-n junction isolation “Bp30-40”

Application, features: Small-scaleintegrationdigital-analogueIC, VDD< 40 V NPNtransistor vertical: bn =150 Uce=48 V РNP transistor lateral: bр =65 Uсе=60 V РNP transistorvertical: bр =60 Uсе=60 V Capacitors:emitter-base; collector-base; Ме-n+; Ме1-Ме2. Resistors in layers: Isolation; Base; Resistor. PolySi
Process Description: Number of masks, pcs. 8-13 Mean design rule,µm 8.0 Substrate: Si/B-doped/ p-type/Thk 460/Res 10/ (111) Buried layers: Si/Sb-doped/ n-type/Thk 6.0/Res20; Si/B-doped/ p-type/Thk 1.95/Res210 ; Epi layer: Si/P-doped/ n-type/Thk 13/ Res 3.5; Isolation: p-n junction p-base depth, µm 2.0 N+emitter depth, µm 1.7 Emitter size, µm 9*9 Distance between transistors, mm 4 Switching: contacts 1, µm 3*3 space line Me 1, µm 9.0 contacts 2, µm 4*4 space line Me 2, µm 14.0

20 V,p-n junction isolation “Bp30С-20” complementary

Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V NPN transistor vertical: bn=150 Uce=27 V РNP transistor lateral: bр=30 Uсе=35 V РNP transistor vertical: bр=45 Uсе=35 V РNP Vertical with isolated collector: bр=80 Uсе=30 V Capacitors:emitter-base; collector base; Ме-n+; Ме1-Ме2. Resistors in layers: Isolation; Base; Resistor
Process Description: Number of masks, pcs. 12-14 Mean design rule,µm 6.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111) Buried layers: Si/Sb-doped/n-type/Thk 6.0/Res 20; Si/ B-doped/p-type/Thk 1.95/Res 210; Epi layer: Si/P-doped/ n-type/ Thk 8/ Res 1.5; Isolation: p-n junction p-base depth, µm 2.0 N+emitter depth, µm 1.7 Emitter size, µm 7*7 Distance between transistors, µm 4 Switching: contacts 1, µm 3*3 space line Me 1, µm 9.0 contacts 2, µm 4*4 space line Me 2, µm 12.0

0 V, p-n junction isolation “Bp30-20”

Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V NPN transistor vertical: bn=150 Uce=28 V РNP transistor lateral: bр=35 Uсе=45 V РNP transistor vertical: bр=35 Uсе=45 V I2L gate Capacitors:emitter-base; collector-base; Ме-n+; Ме1-Ме2. Resistors in layers: Isolation; Base; Resistor
Process Description: Number of masks, pcs. 8-13 Mean design rule,µm 6.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111) Buried layers: Si/ Sb-doped/ n-type/Thk 6.0/Res 20; Si/ B-doped /p-type/Thk 1.95/Res210; Epi layer: Si/ P-doped/ n-type/ Thk 9/ Res 2.0; Isolation: p-n junction p-base depth, µm 2.2 N+emitter depth, µm 1.7 Emitter size, µm 9*9 Distance between transistors, µm 4 Switching: contacts 1, µm 3*3 space line Me 1, µm 9.0 contacts 2, µm 4*4 space line Me 2, µm 12.0

20 V, p-n junction isolation

Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V NPN Vertical: bn=150 Uce=28 V РNP Lateral: bр=35 Uсе=45 V РNP Vertical: bр=35 Uсе=45 V I2L gate Capacitors:emitter-base; collector-base; Ме-n+; Ме1-Ме2. Resistors in layers: Isolation; Base; Resistor
Process Description: Number of masks, pcs. 13 Mean design rule,µm 6.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111) Buried layers: Si/Sb-doped/ n-type/Thk 5/Res 17; Si/B-doped/ p-type/Thk 1.6/Res510; Epi layer: Si/P-doped/ N-type/ Thk 10/ Res 1.25; Isolation: p-n junction p-base depth, µm 2.4 N+emitter depth, µm 1.7 Emitter size, µm 6 Distance between transistors, µm 6 Switching: contacts 1, µm 4 space line Me 1, µm 13.0 contacts 2, µm 4*4 space line Me 2, µm 12.0

Bipolar technology for the manufacture of transistors, triacs

Application, features: IT (on-state) = 2,0 A Ubr = (600-800)V
Process Description: Substrate: Si/ P-irradiated / Res 35 10 masks (contact, two-side) Base: boron diffusion, depth, µm 35-45 Cathode : phosphorous diffusion, depth, µm 15-18 p-n junction protection: SiPOS, Si3N4, medium temp. PSG Metallization : Al 2,0 mm Passivation: low temp. PSG, Si3N4 Backside: Ti-Ni-Ag

Bipolar technology for the manufacture of npn-transistors with the range of operating voltages: 200-300 V

Application, features: UCB = (250-300) V UCE = (200-250) V Ic= (0,4-0,5) A h21E >40
Process Description: Epi structure Substrate: Si/B-doped/ p-type/ Res 0,03/ (111): Thickness of Epi layer, µm 40-45 Resistivity, Ohm/cm 40-50 7 masks (contact) Base:Phosphorous ion implantation, depth, µm 3-5,5 Emitter: boron diffusion collector-base p-n junction protection : SiPOS Metallization : Al 1,4 µm Backside: Ti-Ni-Sn-Pb-Sn

5 V, «Isoplanar – 1» “BpI-30-5”

Application, features: Small and medium-scale integration digital-analogue IC, VDD < 5V NPN transistor vertical: bn =100 Uсе= 8 V PNP transistor lateral: bр =25 Uce=20 V Resistors in layer: Base
Process Description: Number of masks, pcs. 15 Mean design rule,µm 3.0 Substrate: Si/B-doped/ p-type/Thk 460/Res 10/ (111); Buried layers: Si/Sb-doped/ n-type/Thk 2.5/Res 35; Si/ B-doped/ p-type/Thk 1.95/Res210; Epi layer: Si/P-doped/ n-type/Thk 1.5/Res 0.3; Isolation: LOCOS + p+ - guard rings p-base depth, µm 0.854 N+ emitter depth, µm 0.55 Emitter size, µm 2*3 Distance between transistors, µm 2 Switching: contacts 1, µm 2*3 space line Me 1, µm 6.5 contacts 2 , µm 4*4 space line Me 2, µm 10.0

15 V, p-n junction isolation

Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V NPN Vertical: bn=150 Uce=28 V РNP Lateral: bр=35 Uсе=45 V РNP Vertical: bр=35 Uсе=45 V Capacitor:Ме-n+emitter Resistors in PolySi layer
Process Description: Number of masks, pcs. 10-13 Mean design rule,µm 6.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111) Buried layers: Si/Sb-doped/ n -type/Thk 6.0/Res 20; Si/B-doped/ p-type/Thk 1.95/Res210; Epi layer: Si/ P-doped/ n-type/ Thk 8/ Res 4.5; Isolation: p-n junction p-base depth, µm 2.4 N+emitter depth, µm 1.7 Emitter size, µm 6 Distance between transistors, µm 6 Switching: contacts 1, µm 4 space line Me 1, µm 13

Bipolar technology for high-power npn-transistors manufacturing with the range of operating voltages: 160-300 V

Application, features: UCB = (160-300) V UCE = (160-300) V Ic= (0,1-1,5) A h21E > 25
Process Description: Epi structure: Substrate: Si/Sb-doped/ n-type/Res 0,01 (111): Thickness of Epi layer, µm 35,50 Resistivity, Ohm/cm 23 7-8 masks (contact) Base: ion implantation, depth, µm 2,8-4,6 Emitter: diffusion, depth, µm 1,4-2,8 collector-base p-n junction protection: SiPOS Metallization : Al 1,4 µm Backside: Ti-Ni-Ag (Sn-Pb-Sn) Passivation: low temp. PSG