基础工艺流程

基础工艺流程

Bipolar technology for the manufacture of npn-transistors with the range of collector current: 7,5÷16 A

  • Application, features: UCB = (80-160) V<br /><br />UCE = (30-90) V<br /><br /> Ic= (7,5-16) A<br /><br />h21E >15
  • Process Description: Epi structure<br /><br />Substrate:                       Si/B-doped/ p-type/ Res 0,05/ (111):<br /><br />Thickness of Epi layer, µm                                               25-28<br /><br />Resistivity, Ohm/cm                                                              8-11<br /><br />7 masks (contact)<br /><br />Base:Phosphorous ion implantation, depth, µm       4,5-7,5                                                     <br /><br />Emitter: boron  diffusion,  depth, µm                            1,4-2,5<br /><br />p-n junction protection :                                       SiO2, Ta2,O5<br /><br />Metallization :                                                              Al  4, 0 µm<br /><br />Backside:                                                                         Ti-Ni-Ag

Bipolar technology for the manufacture of npn-transistors with the range of operating voltages: 200-300 V

  • Application, features: UCB = (250-300) V<br /><br />UCE = (200-250) V<br /><br /> Ic= (0,4-0,5) A<br /><br /> h21E >40
  • Process Description: Epi structure<br /><br />Substrate:                       Si/B-doped/ p-type/ Res 0,03/  (111):<br /><br />Thickness of Epi layer, µm                                                40-45<br /><br />Resistivity, Ohm/cm                                                            40-50<br /><br />7 masks (contact)<br /><br />Base:Phosphorous ion implantation, depth, µm           3-5,5                                                        <br /><br />Emitter: boron diffusion<br /><br />collector-base p-n junction protection :                          SiPOS<br /><br />Metallization :                                                                 Al 1,4 µm<br /><br />Backside:                                                             Ti-Ni-Sn-Pb-Sn

40 V, p-n junction isolation “Bp30-40”

  • Application, features: Small-scaleintegrationdigital-analogueIC, VDD< 40 V<br /><br /> <br /><br />NPNtransistor vertical:<br /><br />bn =150 Uce=48 V<br /><br />РNP transistor lateral:<br /><br />bр =65 Uсе=60 V<br /><br />РNP transistorvertical:<br /><br />bр =60 Uсе=60 V<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor.<br /><br />PolySi
  • Process Description: Number of masks, pcs.                                                       8-13<br /><br />Mean design rule,µm                                                              8.0<br /><br />Substrate:            Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                Si/Sb-doped/ n-type/Thk 6.0/Res20;<br /><br />                                    Si/B-doped/ p-type/Thk 1.95/Res210 ;<br /><br />Epi layer:                       Si/P-doped/ n-type/Thk 13/ Res 3.5;<br /><br />Isolation:                                                    p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      9*9<br /><br />Distance between transistors, mm                                        4<br /><br />Switching:<br /><br />contacts 1, µm                                                                         3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts 2, µm                                                                        4*4<br /><br />space line Me 2, µm                                                            14.0

0 V, p-n junction isolation “Bp30-20”

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP transistor lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP transistor  vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                  8-13<br /><br />Mean design rule,µm                                                        6.0<br /><br />Substrate:      Si/B-doped/ p-type/ Thk 460/ Res 10/  (111)<br /><br />Buried layers:           Si/ Sb-doped/ n-type/Thk 6.0/Res 20;<br /><br />                                 Si/ B-doped /p-type/Thk 1.95/Res210;<br /><br />Epi layer:                     Si/ P-doped/ n-type/ Thk 9/ Res 2.0;<br /><br />Isolation:                                                 p-n junction<br /><br />p-base depth, µm                                                              2.2<br /><br />N+emitter depth, µm                                                         1.7<br /><br />Emitter size, µm                                                                9*9<br /><br />Distance between transistors, µm                                    4<br /><br />Switching:  <br /><br />contacts 1, µm                                                                   3*3<br /><br />space line  Me 1, µm                                                         9.0<br /><br />contacts  2, µm                                                                  4*4<br /><br />space line Me 2, µm                                                       12.0

Field P DMOS transistors

  • Av (V/mV) Min: 4
  • Battery Current, IBAT1 (max), nA: 4
  • Battery Supply Voltage, VBAT: 4
  • External Caps (mF): 4
  • Features: 3
  • Frequency, kHz: 2
  • FT, МHz: 1
  • Functions: 12H/24H: 1
  • Process Description: Number of masks, pcs.                                             7-9<br /><br />Min design rule,µm                                                     3.0<br /><br />Substrate:                      Si/B-doped/ p-type/Res 0,005<br /><br />Epi layer: <br /><br />thickness                                                        (15-34) µm<br /><br />Resistivity                                               (2÷21) Ohm/cm<br /><br />Gate oxide                                                  (42,5÷80) nm<br /><br />Interlayer dielectric                        medium temp. PSG <br /><br />Passivation:                                            low temp. PSG 
  • U меж.баз., В (max): 324
  • Ucc ЖКИ,В: 23423
  • Uds, В: 4324
  • Ui max, В: 324
  • Uo, В: 32423
  • Uref, В, (max): 423
  • Uref, В, (min): 423
  • The prototype: UT54ACS164245

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

  • Application, features: MOSFET<br /><br />NMOS: Vtn=2÷4 V<br /><br />Umax= 60÷900 V
  • Process Description: Number of masks, pcs.                                                8<br /><br />Min design rule,µm                                                    2.0<br /><br />Substrate:                  Si/Sb-doped/ n-type/Res 0,015; <br /><br />                                   Si/ As-doped/ n-type/ Res 0,003<br /><br />Epi layer:<br /><br />thickness                                                         8÷75) µm<br /><br />Resistivity                                     (0,67÷31,5) Ohm/cm<br /><br />Gate oxide                                                  (60÷100) nm<br /><br />Interlayer dielectric       medium temp. oxide + BPSG <br /><br />Passivation                                    PEoxide + PE SI3N4

1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link

  • Application, features: CMOS master-slice chip<br /><br /> NMOS: <br /><br />Vtn=1.0 V, Ic >10 mA. Ubr>12V<br /><br /> <br /><br />PMOS: <br /><br />Vtр=1.0 V, Ic >4.0 mA, Ubr>12V
  • Process Description: Number of masks, pcs.                                              11<br /><br />Design rule,µm                                                        1.2<br /><br />Substrate:                            Si/B-doped / p-type/Res 12<br /><br />N/P-well depth, µm                                                  5/6<br /><br />Gate SiO2, Å                                                    250-300<br /><br />Interlayer dielectric:                                            BPSG<br /><br />Channel length: NMOS/PMOS, µm                         2.0<br /><br />Contacts, µm                                                     2.0x2.0<br /><br />Space line Me1, µm                                                    8<br /><br />Space line Me 2, µm                                                  10

5 V, 1.5 µm CMOS, 1 PolySi, 1 Me, 150mm wafers

  • Application, features: Digital IMC, microcontrollers with VDD= 5V<br /><br /> <br /><br />NMOS: Vtn= 0.6V, Usd >10 V<br /><br />PMOS: Vtp= 1.0V, Usd >13 V
  • Process Description: Number of masks, pcs.                                                    16<br /><br />Design rule,µm                                                                 1.5<br /><br />Substrate:                 Si/B-doped/ p-type/Res 12      2 wells                                               <br /><br />N/P-well depth, µm                                                           5/6<br /><br />Interlayer dielectric:                                                      BPSG<br /><br />Gate SiO2, Å                                                                     250<br /><br />Interlayer dielectric:                                                     BPSG<br /><br />Transistor built in ROM<br /><br />Buried contacts<br /><br />Channel length: NMOS/PMOS, µm                               1.5<br /><br /> N &amp; P LDD- drains<br /><br />space line PolySi,µm                                                       2.5<br /><br />contacts, µm                                                                  Ø 1.5<br /><br />space line Me,µm                                                             3.5  

20 V, p-n junction isolation

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                         13<br /><br />Mean design rule,µm                                                            6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 5/Res 17;<br /><br />                                        Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                    Si/P-doped/ N-type/ Thk 10/ Res 1.25;<br /><br />Isolation:                                                                  p-n junction<br /><br />p-base depth, µm                                                                   2.4<br /><br />N+emitter depth, µm                                                              1.7<br /><br />Emitter size, µm                                                                         6<br /><br />Distance between transistors, µm                                         6<br /><br />Switching: <br /><br />contacts 1, µm                                                                            4<br /><br />space line  Me 1, µm                                                           13.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line Me 2, µm                                                             12.0

15 V, p-n junction isolation

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />Capacitor:Ме-n+emitter<br /><br />Resistors in PolySi layer
  • Process Description: Number of masks, pcs.                                                    10-13<br /><br />Mean design rule,µm                                                             6.0<br /><br />Substrate:          Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers:              Si/Sb-doped/ n -type/Thk 6.0/Res 20;<br /><br />                                       Si/B-doped/ p-type/Thk 1.95/Res210;<br /><br />Epi layer:                          Si/ P-doped/ n-type/ Thk 8/ Res 4.5;<br /><br />Isolation:                                                                   p-n junction<br /><br />p-base depth, µm                                                                    2.4<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                          6<br /><br />Distance between transistors, µm                                          6<br /><br />Switching: <br /><br />contacts 1, µm                                                                             4<br /><br />space line  Me 1, µm                                                                13

Bipolar technology for the manufacture of transistors, triacs

  • Application, features: IT (on-state) = 2,0 A<br /><br />Ubr = (600-800)V
  • Process Description: Substrate:                                            Si/ P-irradiated / Res 35<br /><br />10 masks (contact, two-side)<br /><br />Base: boron diffusion,<br /><br />depth, µm                                                                             35-45<br /><br />Cathode : phosphorous diffusion,<br /><br />depth, µm                                                                             15-18<br /><br />p-n junction protection:  SiPOS, Si3N4, medium temp. PSG<br /><br />Metallization :                                                               Al 2,0 mm<br /><br />Passivation:                                             low temp. PSG, Si3N4<br /><br />Backside:                                                                           Ti-Ni-Ag

Field N DMOS transistors

  • Application, features: MOSFET

    Low-power

    Vtn= 0,6-3,0V

    Ubr=50-200V

    Pmax=1,0 Watt

     

    High-power

    Vtn= 2,0-4,0V

    Ubr=50-600V

    Pmax=200 Watt
  • Process Description: Number of masks, pcs.                                              7-9<br /><br />Min design rule,µm                                                      3.0<br /><br />Substrate:                        Si/Sb-doped/ n-type/Res 0,01<br /><br />Epi layer: <br /><br />Thickness                                                          (9÷42) µm<br /><br />Resistivity                                              (0,7÷16) Ohm/cm<br /><br />Gate oxide                                                    (42,5÷80) nm<br /><br />Interlayer dielectric -                        medium temp. PSG <br /><br />Passivation:                                               low temp. PSG 

5 V, «Isoplanar – 1» “BpI-30-5”

  • Application, features: Small and medium-scale  integration digital-analogue IC, VDD < 5V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn =100 Uсе= 8 V<br /><br />PNP transistor lateral:<br /><br />bр =25 Uce=20 V<br /><br /> <br /><br />Resistors in layer: Base
  • Process Description: Number of masks, pcs.                                           15<br /><br />Mean design rule,µm                                            3.0<br /><br />Substrate:         Si/B-doped/ p-type/Thk 460/Res 10/ (111);<br /><br />Buried layers:             Si/Sb-doped/ n-type/Thk 2.5/Res 35;<br /><br />                                Si/ B-doped/ p-type/Thk 1.95/Res210;<br /><br />Epi layer: Si/P-doped/ n-type/Thk 1.5/Res 0.3;<br /><br />Isolation: LOCOS + p+ - guard rings<br /><br />p-base depth, µm                                                0.854<br /><br />N+ emitter depth, µm                                          0.55<br /><br />Emitter size, µm                                                   2*3<br /><br />Distance between transistors, µm                            2                                <br /><br /> Switching:<br /><br />contacts 1, µm                                                       2*3<br /><br />space line Me  1, µm                                            6.5             <br /><br />contacts 2 , µm                                                     4*4<br /><br />space line Me 2, µm                                           10.0

Bipolar technology for high-power npn-transistors manufacturing with the range of operating voltages: 160-300 V

  • Application, features: UCB = (160-300) V<br /><br />UCE = (160-300) V<br /><br /> Ic= (0,1-1,5) A<br /><br /> h21E > 25
  • Process Description: Epi structure:<br /><br />Substrate:                        Si/Sb-doped/ n-type/Res 0,01 (111):<br /><br />Thickness of Epi layer, µm                                                  35,50<br /><br />Resistivity, Ohm/cm                                                                   23<br /><br />7-8 masks (contact)<br /><br />Base: ion implantation, depth, µm                                  2,8-4,6<br /><br />Emitter: diffusion, depth, µm                                             1,4-2,8<br /><br />collector-base p-n junction protection:                             SiPOS<br /><br />Metallization :                                                                 Al     1,4 µm<br /><br />Backside:                                                         Ti-Ni-Ag (Sn-Pb-Sn)<br /><br />Passivation:                                                              low temp. PSG