基础工艺流程

基础工艺流程

5 V, 3 µm CMOS, 1 PolySi, 1 Me

  • Application, features: Small and medium-scale integration logic IC, VDD < 5 V<br /><br /> <br /><br /> NMOS: <br /><br />Vtn=0.8-1.2 V, Ic >4 mA. Ubr>8V<br /><br />PMOS: <br /><br />Vtр=0.8-1.2 V, Ic >2 mA, Ubr>8V
  • Process Description: Number of masks, pcs.                                          11<br /><br />Design rule,µm                                                    2.0<br /><br />Substrate:                       Si/P-doped/ n-type/Res 4.5<br /><br />N/P-wells depth, µm                                            6-8<br /><br />Gate SiO2, Å                                              425 / 300<br /><br />Interlayer dielectric:                                        BPSG<br /><br />Channel length: NMOS/PMOS, µm                     3-4<br /><br />Space line PolySi, µm                                           10<br /><br />Contacts, µm                                                       4*4<br /><br />Space line Me, µm                                                10

1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate

  • Application, features: Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA<br /><br />PMOS: <br /><br />Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
  • Process Description: Number of masks, pcs.                                          9<br /><br />Design rules,µm                                            3,0-5,0<br /><br />Substrate:                    Si/P-doped/ n-type/Res 4.5<br /><br />P-well depth, µm                                                   6-8<br /><br />Gate SiO2, Å                                                          800<br /><br />Interlayer dielectric:                 medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm                       3<br /><br />Space line PolySi, µm                                           10<br /><br />Contacts , µm                                                            5<br /><br />Space line Me, µm                                                 12

CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer

  • Application, features: Digital IC,<br /><br />Epitaxy =2.4¸6.0 V<br /><br /> <br /><br />For 3.0 V<br /><br />NMOS: Vtn=0.6 V, Usd >5 V<br /><br />PMOS: Vtр=-0.6 V, Usd >5 V<br /><br />For 5.0 V<br /><br />NMOS: Vtn=1.0 V, Usd >8 V<br /><br />PMOS: Vtр=-0.9 V, Usd >8 V
  • Process Description: Number of photolithographies, pcs.            22<br /><br />Design rule, μm                                        0.35<br /><br />Substrate:                         725KDB0,015(100)<br /><br />Epitaxial layer:                                15KDB12<br /><br />2 retrograde wells for high-voltage transistors<br /><br />2 retrograde wells for low-voltage transistors<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm        1.05 μm<br /><br />Gate SiO2, Å    70 for low-voltage transistors<br /><br />                        350 for high-voltage transistors<br /><br />Channel length<br /><br />NMOS/PMOS, μm     0.35 for low-voltage<br /><br />                                    transistors<br /><br />NMOS/PMOS, μm     1.0 for high-voltage<br /><br />                                    transistors                                               <br /><br />N&amp;P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I,2                                Ti/AlCu / Ti /TiN<br /><br />Contacts 1 (W-filled), μm                        ø 0.4<br /><br />Metal 1 pitch, μm                                    0.95<br /><br />Metal                                                  Ti/AlCu<br /><br />Contacts 2,3 (W-filled), μm                      ø 0.5<br /><br />Metal 2 pitch, μm                                      1.1

15 V, p-n junction isolation

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />Capacitor:Ме-n+emitter<br /><br />Resistors in PolySi layer
  • Process Description: Number of masks, pcs.                                                    10-13<br /><br />Mean design rule,µm                                                             6.0<br /><br />Substrate:          Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers:              Si/Sb-doped/ n -type/Thk 6.0/Res 20;<br /><br />                                       Si/B-doped/ p-type/Thk 1.95/Res210;<br /><br />Epi layer:                          Si/ P-doped/ n-type/ Thk 8/ Res 4.5;<br /><br />Isolation:                                                                   p-n junction<br /><br />p-base depth, µm                                                                    2.4<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                          6<br /><br />Distance between transistors, µm                                          6<br /><br />Switching: <br /><br />contacts 1, µm                                                                             4<br /><br />space line  Me 1, µm                                                                13

Bipolar technology for the manufacture of npn-transistors with the range of collector current: 7,5÷16 A

  • Application, features: UCB = (80-160) V<br /><br />UCE = (30-90) V<br /><br /> Ic= (7,5-16) A<br /><br />h21E >15
  • Process Description: Epi structure<br /><br />Substrate:                       Si/B-doped/ p-type/ Res 0,05/ (111):<br /><br />Thickness of Epi layer, µm                                               25-28<br /><br />Resistivity, Ohm/cm                                                              8-11<br /><br />7 masks (contact)<br /><br />Base:Phosphorous ion implantation, depth, µm       4,5-7,5                                                     <br /><br />Emitter: boron  diffusion,  depth, µm                            1,4-2,5<br /><br />p-n junction protection :                                       SiO2, Ta2,O5<br /><br />Metallization :                                                              Al  4, 0 µm<br /><br />Backside:                                                                         Ti-Ni-Ag

20 V,p-n junction isolation “Bp30С-20” complementary

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor  vertical:<br /><br />bn=150 Uce=27 V<br /><br />РNP transistor  lateral:<br /><br />bр=30 Uсе=35 V<br /><br />РNP transistor  vertical:<br /><br />bр=45 Uсе=35 V<br /><br />РNP Vertical with isolated collector:<br /><br />bр=80 Uсе=30 V<br /><br />Capacitors:emitter-base; collector base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                     12-14<br /><br />Mean design rule,µm                                                              6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/  (111)<br /><br />Buried layers:                Si/Sb-doped/n-type/Thk 6.0/Res  20;<br /><br />                                    Si/ B-doped/p-type/Thk 1.95/Res    210;<br /><br />Epi layer:                       Si/P-doped/ n-type/ Thk 8/ Res     1.5;<br /><br />Isolation:                                                   p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      7*7<br /><br />Distance between transistors, µm                                         4<br /><br />Switching: <br /><br />contacts 1, µm                                                                        3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line  Me 2, µm                                                           12.0

20 V, p-n junction isolation

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                         13<br /><br />Mean design rule,µm                                                            6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 5/Res 17;<br /><br />                                        Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                    Si/P-doped/ N-type/ Thk 10/ Res 1.25;<br /><br />Isolation:                                                                  p-n junction<br /><br />p-base depth, µm                                                                   2.4<br /><br />N+emitter depth, µm                                                              1.7<br /><br />Emitter size, µm                                                                         6<br /><br />Distance between transistors, µm                                         6<br /><br />Switching: <br /><br />contacts 1, µm                                                                            4<br /><br />space line  Me 1, µm                                                           13.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line Me 2, µm                                                             12.0

0 V, p-n junction isolation “Bp30-20”

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP transistor lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP transistor  vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                  8-13<br /><br />Mean design rule,µm                                                        6.0<br /><br />Substrate:      Si/B-doped/ p-type/ Thk 460/ Res 10/  (111)<br /><br />Buried layers:           Si/ Sb-doped/ n-type/Thk 6.0/Res 20;<br /><br />                                 Si/ B-doped /p-type/Thk 1.95/Res210;<br /><br />Epi layer:                     Si/ P-doped/ n-type/ Thk 9/ Res 2.0;<br /><br />Isolation:                                                 p-n junction<br /><br />p-base depth, µm                                                              2.2<br /><br />N+emitter depth, µm                                                         1.7<br /><br />Emitter size, µm                                                                9*9<br /><br />Distance between transistors, µm                                    4<br /><br />Switching:  <br /><br />contacts 1, µm                                                                   3*3<br /><br />space line  Me 1, µm                                                         9.0<br /><br />contacts  2, µm                                                                  4*4<br /><br />space line Me 2, µm                                                       12.0

200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors

  • Application, features: Small -scale integration analogue IC, <br /><br />VDD <  210 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn =70 Uсе=50 V<br /><br />NDMOS: Vtn= 2.0 V,<br /><br />Usd >200 V<br /><br />PDMOS: Vtp= -1.0 V,<br /><br />Usd >200 V<br /><br />NMOS: Vtn= 1.5V, Usd >20V<br /><br /> <br /><br />Resistors in layer:<br /><br />NPN base, Р-drain, PolySi.<br /><br /> <br /><br />Capacitors: PolySi-Si (SiO2 900 Å)<br /><br />PolySi-Al (SiO2 1600 Å)
  • Process Description: Number of masks, pcs.                                            19<br /><br />Min design rule,µm                                             4.0<br /><br />Substrate:        Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers:            Si/Sb-doped/ n-type/Thk 30/Res 5.5;<br /><br />                                  Si/B-doped/ p-type/Thk 300/Res2.0 ; <br /><br />Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0;<br /><br />Isolation:                                                    p-n junction<br /><br />P-well depth, µm                                                      6.5<br /><br />NDMOS base depth, µm                                          3.0<br /><br />Gate SiO2, Å                                                           900<br /><br />NPN p-base depth, µm                                             2.5<br /><br />N+emitter depth, µm                                                0.8<br /><br />Interlayer dielectric –  medium temp. PSG<br /><br />0,55mm +SIPOS 0.1µm + medium temp. PSG    1,1µm<br /><br />Channel length (gate):<br /><br />N/PDMOS, µm                                                            6                                            <br /><br />Space line PolySi, µm                                                 8<br /><br />Contacts, µm                                                             Ø4<br /><br />Space line Me, µm                                                      12

15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

  • Application, features: Small and medium-scale integration logic IC, VDD < 20 V<br /><br /> <br /><br />NMOS: Vtn= 1.1 V, Usd >27 V<br /><br />PMOS: Vtp= -1.0 V, Usd >29 V
  • Process Description: Number of masks, pcs.                                           9<br /><br />Design rule,µm                                                    5.0<br /><br />Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100)                                                <br /><br />P-well depth, µm                                                   10<br /><br />Gate SiO2, Å                                                        950<br /><br />Interlayer dielectric:                    medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm                      5/6<br /><br />space line PolySi,µm                                            5.5<br /><br />contacts, µm                                                           Ø2<br /><br />space line  Me, µm                                                   8  

Field P DMOS transistors

  • Av (V/mV) Min: 4
  • Battery Current, IBAT1 (max), nA: 4
  • Battery Supply Voltage, VBAT: 4
  • External Caps (mF): 4
  • Features: 3
  • Frequency, kHz: 2
  • FT, МHz: 1
  • Functions: 12H/24H: 1
  • Process Description: Number of masks, pcs.                                             7-9<br /><br />Min design rule,µm                                                     3.0<br /><br />Substrate:                      Si/B-doped/ p-type/Res 0,005<br /><br />Epi layer: <br /><br />thickness                                                        (15-34) µm<br /><br />Resistivity                                               (2÷21) Ohm/cm<br /><br />Gate oxide                                                  (42,5÷80) nm<br /><br />Interlayer dielectric                        medium temp. PSG <br /><br />Passivation:                                            low temp. PSG 
  • U меж.баз., В (max): 324
  • Ucc ЖКИ,В: 23423
  • Uds, В: 4324
  • Ui max, В: 324
  • Uo, В: 32423
  • Uref, В, (max): 423
  • Uref, В, (min): 423
  • The prototype: UT54ACS164245

40 V, p-n junction isolation “Bp30-40”

  • Application, features: Small-scaleintegrationdigital-analogueIC, VDD< 40 V<br /><br /> <br /><br />NPNtransistor vertical:<br /><br />bn =150 Uce=48 V<br /><br />РNP transistor lateral:<br /><br />bр =65 Uсе=60 V<br /><br />РNP transistorvertical:<br /><br />bр =60 Uсе=60 V<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor.<br /><br />PolySi
  • Process Description: Number of masks, pcs.                                                       8-13<br /><br />Mean design rule,µm                                                              8.0<br /><br />Substrate:            Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                Si/Sb-doped/ n-type/Thk 6.0/Res20;<br /><br />                                    Si/B-doped/ p-type/Thk 1.95/Res210 ;<br /><br />Epi layer:                       Si/P-doped/ n-type/Thk 13/ Res 3.5;<br /><br />Isolation:                                                    p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      9*9<br /><br />Distance between transistors, mm                                        4<br /><br />Switching:<br /><br />contacts 1, µm                                                                         3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts 2, µm                                                                        4*4<br /><br />space line Me 2, µm                                                            14.0

Field N DMOS transistors

  • Application, features: MOSFET

    Low-power

    Vtn= 0,6-3,0V

    Ubr=50-200V

    Pmax=1,0 Watt

     

    High-power

    Vtn= 2,0-4,0V

    Ubr=50-600V

    Pmax=200 Watt
  • Process Description: Number of masks, pcs.                                              7-9<br /><br />Min design rule,µm                                                      3.0<br /><br />Substrate:                        Si/Sb-doped/ n-type/Res 0,01<br /><br />Epi layer: <br /><br />Thickness                                                          (9÷42) µm<br /><br />Resistivity                                              (0,7÷16) Ohm/cm<br /><br />Gate oxide                                                    (42,5÷80) nm<br /><br />Interlayer dielectric -                        medium temp. PSG <br /><br />Passivation:                                               low temp. PSG 

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

  • Application, features: MOSFET<br /><br />NMOS: Vtn=2÷4 V<br /><br />Umax= 60÷900 V
  • Process Description: Number of masks, pcs.                                                8<br /><br />Min design rule,µm                                                    2.0<br /><br />Substrate:                  Si/Sb-doped/ n-type/Res 0,015; <br /><br />                                   Si/ As-doped/ n-type/ Res 0,003<br /><br />Epi layer:<br /><br />thickness                                                         8÷75) µm<br /><br />Resistivity                                     (0,67÷31,5) Ohm/cm<br /><br />Gate oxide                                                  (60÷100) nm<br /><br />Interlayer dielectric       medium temp. oxide + BPSG <br /><br />Passivation                                    PEoxide + PE SI3N4