基础工艺流程

基础工艺流程

5 V, 3 µm CMOS, 1 PolySi, 1 Me

  • Application, features: Small and medium-scale integration logic IC, VDD < 5 V<br /><br /> <br /><br /> NMOS: <br /><br />Vtn=0.8-1.2 V, Ic >4 mA. Ubr>8V<br /><br />PMOS: <br /><br />Vtр=0.8-1.2 V, Ic >2 mA, Ubr>8V
  • Process Description: Number of masks, pcs.                                          11<br /><br />Design rule,µm                                                    2.0<br /><br />Substrate:                       Si/P-doped/ n-type/Res 4.5<br /><br />N/P-wells depth, µm                                            6-8<br /><br />Gate SiO2, Å                                              425 / 300<br /><br />Interlayer dielectric:                                        BPSG<br /><br />Channel length: NMOS/PMOS, µm                     3-4<br /><br />Space line PolySi, µm                                           10<br /><br />Contacts, µm                                                       4*4<br /><br />Space line Me, µm                                                10

Bipolar technology for the manufacture of positive and negative polarity voltage regulators, two metallization levels

  • Application, features: NPN Vertical:<br /><br />h 21E =(80-200)<br /><br />UCE >=18 V<br /><br />PNP Lateral:<br /><br />h 21E>=40<br /><br />UCE >=20V<br /><br />Capacitor: n+ - Al<br /><br />Resistors in layer:<br /><br />Base; resistor
  • Process Description: Number of masks, pcs.                                                                   11-13<br /><br />Mean design rule,µm                                                                            4-5<br /><br />Substrate:                           Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                                    Si/Sb-doped/ n-type/Thk5/Res17;<br /><br />                                                         Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                                      Si/P-doped/ n-type/Thk 10/ Res 1,25;<br /><br />Isolation:                                                                                   p-n junction<br /><br />Deep collector, separation and emitter layers have been carried out by method of diffusion.<br /><br />Base, resistor layers – by method of ion implantation<br /><br />Capacitor dielectric:                                                 Si oxide or Si nitride<br /><br />p-base depth, µm                                                                           1,8÷2,8<br /><br />N+emitter depth, µm                                                                      0,9÷2,2<br /><br />The first interlayer dielectric:        medium temperature PSG+ Si3N4<br /><br />The second interlayer dielectric:                        low temperature PSG<br /><br />The first  metallization level                                        AlSiCuTi  0,55 µm<br /><br />The second metallization level                                    AlSi, Al      1,4 µm<br /><br />Passivation:                                                         low temp. PSG   1,0 µm

5 V, «Isoplanar – 1» “BpI-30-5”

  • Application, features: Small and medium-scale  integration digital-analogue IC, VDD < 5V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn =100 Uсе= 8 V<br /><br />PNP transistor lateral:<br /><br />bр =25 Uce=20 V<br /><br /> <br /><br />Resistors in layer: Base
  • Process Description: Number of masks, pcs.                                           15<br /><br />Mean design rule,µm                                            3.0<br /><br />Substrate:         Si/B-doped/ p-type/Thk 460/Res 10/ (111);<br /><br />Buried layers:             Si/Sb-doped/ n-type/Thk 2.5/Res 35;<br /><br />                                Si/ B-doped/ p-type/Thk 1.95/Res210;<br /><br />Epi layer: Si/P-doped/ n-type/Thk 1.5/Res 0.3;<br /><br />Isolation: LOCOS + p+ - guard rings<br /><br />p-base depth, µm                                                0.854<br /><br />N+ emitter depth, µm                                          0.55<br /><br />Emitter size, µm                                                   2*3<br /><br />Distance between transistors, µm                            2                                <br /><br /> Switching:<br /><br />contacts 1, µm                                                       2*3<br /><br />space line Me  1, µm                                            6.5             <br /><br />contacts 2 , µm                                                     4*4<br /><br />space line Me 2, µm                                           10.0

CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer

  • Application, features: Digital IC with EEPROM,<br /><br />Epitaxy =2.4¸6.0 V<br /><br />For low-voltage transistors<br /><br />NMOS: <br /><br />Vtn=0.5 V, Usd >7 V<br /><br />PMOS: <br /><br />Vtр=-0.6 V, Usd >7 V<br /><br />For high-voltage transistors<br /><br />Vtn=0.6 V, Usd >16 V<br /><br />PMOS: <br /><br />Vtр=-0.6 V, Usd >9 V
  • Process Description: Number of photolithographies, pcs.               27<br /><br />Design rule, μm                                        0.35<br /><br />Substrate:                           725KDB0,015(100)<br /><br />Epitaxial layer:                                  15KDB12<br /><br />2 wells<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm            1.05 μm<br /><br />Gate SiO2, Å                                           250<br /><br />Tunnel oxide, Å                                          75<br /><br />Capacitor dielectric                   Si3N4, Å    250<br /><br />Channel length<br /><br />NMOS/PMOS, μm     0.35 for low-voltage<br /><br />                                    transistors<br /><br />NMOS/PMOS, μm     2.5/1.0 for high-voltage<br /><br />                                    transistors                                              <br /><br />N&amp;P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I,2                               Ti/AlCu / Ti /TiN<br /><br />Contacts 1 (W-filled)                              ø 0.5<br /><br />Metal 1 pitch, μm                                    0.95<br /><br />Metal 3                                              Ti/AlCu<br /><br />Contacts 2,3 (W-filled), μm                     ø 0.5<br /><br />Metal 2 pitch, μm                                      1.1

Bipolar technology for the manufacture of voltage regulators of positive and negative polarity, one metallization level

  • Application, features: NPN  Vertical:<br /><br />h 21E =(100-300)<br /><br />UCE >=38V<br /><br />PNP Lateral:<br /><br />h 21E>=20<br /><br />UCE >=38V<br /><br />Capacitor: n+ - Al<br /><br />Resistors in layer:<br /><br />Base; resistor
  • Process Description: Number of masks, pcs.                                                            7-10<br /><br />Mean design rule,µm                                                                  4-5<br /><br />Substrate:                 Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                           Si/Sb-doped/ n-type/Thk5/Res25;<br /><br />                                       Si/Boron-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer:                            Si/P-doped/ n-type/Thk 13,3/ Res 3.6;<br /><br />Isolation:                                                                          p-n junction<br /><br />p-base depth, µm                                                                  1,8÷2,8<br /><br />N+emitter depth, µm                                                             0,9÷2,2<br /><br />Deep collector, separation and emitter layers have been carried out by method of diffusion<br /><br />Capacitor dielectric:                                        Si oxide or Si nitride<br /><br />Interlayer dielectric:                              medium temperature PSG<br /><br />Metallization:                                                                      Al   1,4 µm<br /><br />Passivation:                                                 low temp. PSG 1,0 µm

40 V, p-n junction isolation “Bp30-40”

  • Application, features: Small-scaleintegrationdigital-analogueIC, VDD< 40 V<br /><br /> <br /><br />NPNtransistor vertical:<br /><br />bn =150 Uce=48 V<br /><br />РNP transistor lateral:<br /><br />bр =65 Uсе=60 V<br /><br />РNP transistorvertical:<br /><br />bр =60 Uсе=60 V<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor.<br /><br />PolySi
  • Process Description: Number of masks, pcs.                                                       8-13<br /><br />Mean design rule,µm                                                              8.0<br /><br />Substrate:            Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers:                Si/Sb-doped/ n-type/Thk 6.0/Res20;<br /><br />                                    Si/B-doped/ p-type/Thk 1.95/Res210 ;<br /><br />Epi layer:                       Si/P-doped/ n-type/Thk 13/ Res 3.5;<br /><br />Isolation:                                                    p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      9*9<br /><br />Distance between transistors, mm                                        4<br /><br />Switching:<br /><br />contacts 1, µm                                                                         3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts 2, µm                                                                        4*4<br /><br />space line Me 2, µm                                                            14.0

20 V,p-n junction isolation “Bp30С-20” complementary

  • Application, features: Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor  vertical:<br /><br />bn=150 Uce=27 V<br /><br />РNP transistor  lateral:<br /><br />bр=30 Uсе=35 V<br /><br />РNP transistor  vertical:<br /><br />bр=45 Uсе=35 V<br /><br />РNP Vertical with isolated collector:<br /><br />bр=80 Uсе=30 V<br /><br />Capacitors:emitter-base; collector base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
  • Process Description: Number of masks, pcs.                                                     12-14<br /><br />Mean design rule,µm                                                              6.0<br /><br />Substrate:         Si/B-doped/ p-type/ Thk 460/ Res 10/  (111)<br /><br />Buried layers:                Si/Sb-doped/n-type/Thk 6.0/Res  20;<br /><br />                                    Si/ B-doped/p-type/Thk 1.95/Res    210;<br /><br />Epi layer:                       Si/P-doped/ n-type/ Thk 8/ Res     1.5;<br /><br />Isolation:                                                   p-n junction<br /><br />p-base depth, µm                                                                    2.0<br /><br />N+emitter depth, µm                                                               1.7<br /><br />Emitter size, µm                                                                      7*7<br /><br />Distance between transistors, µm                                         4<br /><br />Switching: <br /><br />contacts 1, µm                                                                        3*3<br /><br />space line  Me 1, µm                                                              9.0<br /><br />contacts  2, µm                                                                       4*4<br /><br />space line  Me 2, µm                                                           12.0

Field P DMOS transistors

  • Av (V/mV) Min: 4
  • Battery Current, IBAT1 (max), nA: 4
  • Battery Supply Voltage, VBAT: 4
  • External Caps (mF): 4
  • Features: 3
  • Frequency, kHz: 2
  • FT, МHz: 1
  • Functions: 12H/24H: 1
  • Process Description: Number of masks, pcs.                                             7-9<br /><br />Min design rule,µm                                                     3.0<br /><br />Substrate:                      Si/B-doped/ p-type/Res 0,005<br /><br />Epi layer: <br /><br />thickness                                                        (15-34) µm<br /><br />Resistivity                                               (2÷21) Ohm/cm<br /><br />Gate oxide                                                  (42,5÷80) nm<br /><br />Interlayer dielectric                        medium temp. PSG <br /><br />Passivation:                                            low temp. PSG 
  • U меж.баз., В (max): 324
  • Ucc ЖКИ,В: 23423
  • Uds, В: 4324
  • Ui max, В: 324
  • Uo, В: 32423
  • Uref, В, (max): 423
  • Uref, В, (min): 423
  • The prototype: UT54ACS164245

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

  • Application, features: MOSFET<br /><br />NMOS: Vtn=2÷4 V<br /><br />Umax= 60÷900 V
  • Process Description: Number of masks, pcs.                                                8<br /><br />Min design rule,µm                                                    2.0<br /><br />Substrate:                  Si/Sb-doped/ n-type/Res 0,015; <br /><br />                                   Si/ As-doped/ n-type/ Res 0,003<br /><br />Epi layer:<br /><br />thickness                                                         8÷75) µm<br /><br />Resistivity                                     (0,67÷31,5) Ohm/cm<br /><br />Gate oxide                                                  (60÷100) nm<br /><br />Interlayer dielectric       medium temp. oxide + BPSG <br /><br />Passivation                                    PEoxide + PE SI3N4

200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors

  • Application, features: Small -scale integration analogue IC, <br /><br />VDD <  210 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn =70 Uсе=50 V<br /><br />NDMOS: Vtn= 2.0 V,<br /><br />Usd >200 V<br /><br />PDMOS: Vtp= -1.0 V,<br /><br />Usd >200 V<br /><br />NMOS: Vtn= 1.5V, Usd >20V<br /><br /> <br /><br />Resistors in layer:<br /><br />NPN base, Р-drain, PolySi.<br /><br /> <br /><br />Capacitors: PolySi-Si (SiO2 900 Å)<br /><br />PolySi-Al (SiO2 1600 Å)
  • Process Description: Number of masks, pcs.                                            19<br /><br />Min design rule,µm                                             4.0<br /><br />Substrate:        Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers:            Si/Sb-doped/ n-type/Thk 30/Res 5.5;<br /><br />                                  Si/B-doped/ p-type/Thk 300/Res2.0 ; <br /><br />Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0;<br /><br />Isolation:                                                    p-n junction<br /><br />P-well depth, µm                                                      6.5<br /><br />NDMOS base depth, µm                                          3.0<br /><br />Gate SiO2, Å                                                           900<br /><br />NPN p-base depth, µm                                             2.5<br /><br />N+emitter depth, µm                                                0.8<br /><br />Interlayer dielectric –  medium temp. PSG<br /><br />0,55mm +SIPOS 0.1µm + medium temp. PSG    1,1µm<br /><br />Channel length (gate):<br /><br />N/PDMOS, µm                                                            6                                            <br /><br />Space line PolySi, µm                                                 8<br /><br />Contacts, µm                                                             Ø4<br /><br />Space line Me, µm                                                      12

90 V, p-n junction isolation, 1 PolySi, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors

  • Application, features: Small and medium-scale integration analogue IC, VDD <  90 V<br /><br />NPN Vertical:<br /><br />bn =50 Uсе=20 V<br /><br />PNP Lateral:<br /><br />bр =25 Uсе=20 V<br /><br />LNDMOS: Vtn= 2.0 V, Usd >90 V<br /><br />LPDMOS: Vtp= -1.4 V, Usd >90 V<br /><br />NMOS: Vtn= 1.2 V, Usd >18 V<br /><br />PMOS: Vtp= 1.5 V, Usd >18 V<br /><br />VNDMOS: Vtn= 2.0 V, Usd >70 V<br /><br /> <br /><br />Resistors in layer:<br /><br />NDMOS base, Р-drain, PolySi.<br /><br />Capacitors: PolySi-Si (SiO2 750Å)<br /><br />PolySi-Al (SiO2 8000 Å)
  • Process Description: Numberofmasks, pcs.                                             19<br /><br />Min design rule,µm                                              4.0<br /><br />Substrate:          Si/B-doped/  p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers:                  Si/Sb-doped/ n-type/Thk 20/Res 6;<br /><br />                                      Si/B-doped/ p-type/Thk 250/Res2.0 ;<br /><br />Epi layer:                     Si/P-doped/ n-type/ Thk 10/ Res 1.5;<br /><br />Isolation:                                                    p-n junction<br /><br />P-well depth, µm                                                     6.5<br /><br />NDMOS base depth, µm                                         2.5<br /><br />Gate SiO2, Å                                                          750<br /><br />NPN p-base depth, µm                                            2.5<br /><br />N+emitter depth, µm                                               0.5<br /><br />Interlayer dielectric - BPSG, µm                             0,8                                           <br /><br />Channel length (gate):<br /><br />N/PMOS, µm                                                         Ø 4<br /><br />Space line PolySi, µm                                                7<br /><br />Contacts, µm                                                              2<br /><br />Space line Me, µm                                                     8

Field N DMOS transistors

  • Application, features: MOSFET

    Low-power

    Vtn= 0,6-3,0V

    Ubr=50-200V

    Pmax=1,0 Watt

     

    High-power

    Vtn= 2,0-4,0V

    Ubr=50-600V

    Pmax=200 Watt
  • Process Description: Number of masks, pcs.                                              7-9<br /><br />Min design rule,µm                                                      3.0<br /><br />Substrate:                        Si/Sb-doped/ n-type/Res 0,01<br /><br />Epi layer: <br /><br />Thickness                                                          (9÷42) µm<br /><br />Resistivity                                              (0,7÷16) Ohm/cm<br /><br />Gate oxide                                                    (42,5÷80) nm<br /><br />Interlayer dielectric -                        medium temp. PSG <br /><br />Passivation:                                               low temp. PSG 

CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer

  • Application, features: Digital IC,<br /><br />Epitaxy =2.4¸6.0 V<br /><br /> <br /><br />For 3.0 V<br /><br />NMOS: Vtn=0.6 V, Usd >5 V<br /><br />PMOS: Vtр=-0.6 V, Usd >5 V<br /><br />For 5.0 V<br /><br />NMOS: Vtn=1.0 V, Usd >8 V<br /><br />PMOS: Vtр=-0.9 V, Usd >8 V
  • Process Description: Number of photolithographies, pcs.            22<br /><br />Design rule, μm                                        0.35<br /><br />Substrate:                         725KDB0,015(100)<br /><br />Epitaxial layer:                                15KDB12<br /><br />2 retrograde wells for high-voltage transistors<br /><br />2 retrograde wells for low-voltage transistors<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm        1.05 μm<br /><br />Gate SiO2, Å    70 for low-voltage transistors<br /><br />                        350 for high-voltage transistors<br /><br />Channel length<br /><br />NMOS/PMOS, μm     0.35 for low-voltage<br /><br />                                    transistors<br /><br />NMOS/PMOS, μm     1.0 for high-voltage<br /><br />                                    transistors                                               <br /><br />N&amp;P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I,2                                Ti/AlCu / Ti /TiN<br /><br />Contacts 1 (W-filled), μm                        ø 0.4<br /><br />Metal 1 pitch, μm                                    0.95<br /><br />Metal                                                  Ti/AlCu<br /><br />Contacts 2,3 (W-filled), μm                      ø 0.5<br /><br />Metal 2 pitch, μm                                      1.1

Shottky diodes with Mo barrier

  • Application, features: Fast silicon Shottky diodes for switched mode power supplies <br /><br />Urev V   40-150<br /><br />Irev. µa   < 250<br /><br />Idirect max. A   1-30
  • Process Description: Number of masks, pcs.                                                  4<br /><br />Size, mm                                                  0.76x0.76-4x4<br /><br />Substrate: Si/As-doped/ n-type/Thk 460/Res 0.0035 (111)<br /><br />Epi layer:         Si/ P-doped/ n-type/Thk 4.5/Res (0.6-0.8)<br /><br />Isolation:                      p-n junction with field-type oxide<br /><br />Metallization:                                      Al+Mo+Ti-Ni-Ag