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Application, features:
UCB = (60-70) V<br /><br />UCE = (60-70) V<br /><br /> Ic= (2,0-12) A<br /><br /> h21E >500
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Process Description:
Epi structure:<br /><br />Substrate: Si/ B-doped/ p-type/ Res 0,05/ (111):<br /><br />Thickness of the layer, µm 25-33<br /><br />Resistivity, Ohm/cm 10-18<br /><br />6,7 masks (contact)<br /><br />Base: Phosphorous ion implantation,<br /><br />depth, µm 6-8<br /><br />Emitter: boron diffusion,<br /><br />depth, µm 2,5-5,5<br /><br />p-n junction protection : SiO2, Ta2O5<br /><br />Metallization : Al 4, 5 µm<br /><br />Backside: Ti-Ni-Ag
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Application, features:
UCB = (300-350) V<br /><br />UCE = (150-350) V<br /><br /> Ic= (5-15) A<br /><br /> h21E >100
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Process Description:
Epi structure:<br /><br />Substrate: Si/ Sb-doped/ n-type/Res 0,01 (111):<br /><br />Thickness of Epi layer, µm 27-38<br /><br />Resistivity, Ohm/cm 8-21<br /><br />6-7 masks (contact)<br /><br />Base: ion implantation,<br /><br />depth, µm 6-8<br /><br />Emitter: diffusion,<br /><br />depth, µm 2,5-5,5<br /><br />collector-base p-n junction protection : SiPOS<br /><br />Metallization : Al 4, 5 µm<br /><br />Backside: Ti-Ni-Ag<br /><br />Passivation: Low temp. PSG
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Application, features:
Small and medium-scale integration digital-analogue IC, VDD < 5V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn =100 Uсе= 8 V<br /><br />PNP transistor lateral:<br /><br />bр =25 Uce=20 V<br /><br /> <br /><br />Resistors in layer: Base
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Process Description:
Number of masks, pcs. 15<br /><br />Mean design rule,µm 3.0<br /><br />Substrate: Si/B-doped/ p-type/Thk 460/Res 10/ (111);<br /><br />Buried layers: Si/Sb-doped/ n-type/Thk 2.5/Res 35;<br /><br /> Si/ B-doped/ p-type/Thk 1.95/Res210;<br /><br />Epi layer: Si/P-doped/ n-type/Thk 1.5/Res 0.3;<br /><br />Isolation: LOCOS + p+ - guard rings<br /><br />p-base depth, µm 0.854<br /><br />N+ emitter depth, µm 0.55<br /><br />Emitter size, µm 2*3<br /><br />Distance between transistors, µm 2 <br /><br /> Switching:<br /><br />contacts 1, µm 2*3<br /><br />space line Me 1, µm 6.5 <br /><br />contacts 2 , µm 4*4<br /><br />space line Me 2, µm 10.0
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Application, features:
Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
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Process Description:
Number of masks, pcs. 13<br /><br />Mean design rule,µm 6.0<br /><br />Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers: Si/Sb-doped/ n-type/Thk 5/Res 17;<br /><br /> Si/B-doped/ p-type/Thk 1.6/Res510;<br /><br />Epi layer: Si/P-doped/ N-type/ Thk 10/ Res 1.25;<br /><br />Isolation: p-n junction<br /><br />p-base depth, µm 2.4<br /><br />N+emitter depth, µm 1.7<br /><br />Emitter size, µm 6<br /><br />Distance between transistors, µm 6<br /><br />Switching: <br /><br />contacts 1, µm 4<br /><br />space line Me 1, µm 13.0<br /><br />contacts 2, µm 4*4<br /><br />space line Me 2, µm 12.0
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Application, features:
Fast silicon Shottky diodes for switched mode power supplies <br /><br />Urev V 40-150<br /><br />Irev. µa < 250<br /><br />Idirect max. A 1-30
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Process Description:
Number of masks, pcs. 4<br /><br />Size, mm 0.76x0.76-4x4<br /><br />Substrate: Si/As-doped/ n-type/Thk 460/Res 0.0035 (111)<br /><br />Epi layer: Si/ P-doped/ n-type/Thk 4.5/Res (0.6-0.8)<br /><br />Isolation: p-n junction with field-type oxide<br /><br />Metallization: Al+Mo+Ti-Ni-Ag
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Application, features:
Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN transistor vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP transistor lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP transistor vertical:<br /><br />bр=35 Uсе=45 V<br /><br />I2L gate<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor
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Process Description:
Number of masks, pcs. 8-13<br /><br />Mean design rule,µm 6.0<br /><br />Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers: Si/ Sb-doped/ n-type/Thk 6.0/Res 20;<br /><br /> Si/ B-doped /p-type/Thk 1.95/Res210;<br /><br />Epi layer: Si/ P-doped/ n-type/ Thk 9/ Res 2.0;<br /><br />Isolation: p-n junction<br /><br />p-base depth, µm 2.2<br /><br />N+emitter depth, µm 1.7<br /><br />Emitter size, µm 9*9<br /><br />Distance between transistors, µm 4<br /><br />Switching: <br /><br />contacts 1, µm 3*3<br /><br />space line Me 1, µm 9.0<br /><br />contacts 2, µm 4*4<br /><br />space line Me 2, µm 12.0
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Av (V/mV) Min:
4
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Battery Current, IBAT1 (max), nA:
4
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Battery Supply Voltage, VBAT:
4
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External Caps (mF):
4
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Features:
3
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Frequency, kHz:
2
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FT, МHz:
1
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Functions: 12H/24H:
1
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Process Description:
Number of masks, pcs. 7-9<br /><br />Min design rule,µm 3.0<br /><br />Substrate: Si/B-doped/ p-type/Res 0,005<br /><br />Epi layer: <br /><br />thickness (15-34) µm<br /><br />Resistivity (2÷21) Ohm/cm<br /><br />Gate oxide (42,5÷80) nm<br /><br />Interlayer dielectric medium temp. PSG <br /><br />Passivation: low temp. PSG
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U меж.баз., В (max):
324
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Ucc ЖКИ,В:
23423
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Uds, В:
4324
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Ui max, В:
324
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Uo, В:
32423
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Uref, В, (max):
423
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Uref, В, (min):
423
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The prototype:
UT54ACS164245
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Application, features:
Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA<br /><br />PMOS: <br /><br />Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
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Process Description:
Number of masks, pcs. 9<br /><br />Design rules,µm 3,0-5,0<br /><br />Substrate: Si/P-doped/ n-type/Res 4.5<br /><br />P-well depth, µm 6-8<br /><br />Gate SiO2, Å 800<br /><br />Interlayer dielectric: medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm 3<br /><br />Space line PolySi, µm 10<br /><br />Contacts , µm 5<br /><br />Space line Me, µm 12
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Application, features:
Small and medium-scale integration digital-analogue IC, VDD < 18 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn=150 Uce=28 V<br /><br />РNP Lateral:<br /><br />bр=35 Uсе=45 V<br /><br />РNP Vertical:<br /><br />bр=35 Uсе=45 V<br /><br />Capacitor:Ме-n+emitter<br /><br />Resistors in PolySi layer
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Process Description:
Number of masks, pcs. 10-13<br /><br />Mean design rule,µm 6.0<br /><br />Substrate: Si/B-doped/ p-type/ Thk 460/ Res 10/ (111)<br /><br />Buried layers: Si/Sb-doped/ n -type/Thk 6.0/Res 20;<br /><br /> Si/B-doped/ p-type/Thk 1.95/Res210;<br /><br />Epi layer: Si/ P-doped/ n-type/ Thk 8/ Res 4.5;<br /><br />Isolation: p-n junction<br /><br />p-base depth, µm 2.4<br /><br />N+emitter depth, µm 1.7<br /><br />Emitter size, µm 6<br /><br />Distance between transistors, µm 6<br /><br />Switching: <br /><br />contacts 1, µm 4<br /><br />space line Me 1, µm 13
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Application, features:
UCB = (80-160) V<br /><br />UCE = (30-90) V<br /><br /> Ic= (7,5-16) A<br /><br />h21E >15
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Process Description:
Epi structure<br /><br />Substrate: Si/B-doped/ p-type/ Res 0,05/ (111):<br /><br />Thickness of Epi layer, µm 25-28<br /><br />Resistivity, Ohm/cm 8-11<br /><br />7 masks (contact)<br /><br />Base:Phosphorous ion implantation, depth, µm 4,5-7,5 <br /><br />Emitter: boron diffusion, depth, µm 1,4-2,5<br /><br />p-n junction protection : SiO2, Ta2,O5<br /><br />Metallization : Al 4, 0 µm<br /><br />Backside: Ti-Ni-Ag
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Application, features:
MOSFET
Low-power
Vtn= 0,6-3,0V
Ubr=50-200V
Pmax=1,0 Watt
High-power
Vtn= 2,0-4,0V
Ubr=50-600V
Pmax=200 Watt
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Process Description:
Number of masks, pcs. 7-9<br /><br />Min design rule,µm 3.0<br /><br />Substrate: Si/Sb-doped/ n-type/Res 0,01<br /><br />Epi layer: <br /><br />Thickness (9÷42) µm<br /><br />Resistivity (0,7÷16) Ohm/cm<br /><br />Gate oxide (42,5÷80) nm<br /><br />Interlayer dielectric - medium temp. PSG <br /><br />Passivation: low temp. PSG
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Application, features:
Small-scaleintegrationdigital-analogueIC, VDD< 40 V<br /><br /> <br /><br />NPNtransistor vertical:<br /><br />bn =150 Uce=48 V<br /><br />РNP transistor lateral:<br /><br />bр =65 Uсе=60 V<br /><br />РNP transistorvertical:<br /><br />bр =60 Uсе=60 V<br /><br />Capacitors:emitter-base; collector-base; Ме-n+;<br /><br />Ме1-Ме2.<br /><br />Resistors in layers:<br /><br />Isolation; Base; Resistor.<br /><br />PolySi
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Process Description:
Number of masks, pcs. 8-13<br /><br />Mean design rule,µm 8.0<br /><br />Substrate: Si/B-doped/ p-type/Thk 460/Res 10/ (111)<br /><br />Buried layers: Si/Sb-doped/ n-type/Thk 6.0/Res20;<br /><br /> Si/B-doped/ p-type/Thk 1.95/Res210 ;<br /><br />Epi layer: Si/P-doped/ n-type/Thk 13/ Res 3.5;<br /><br />Isolation: p-n junction<br /><br />p-base depth, µm 2.0<br /><br />N+emitter depth, µm 1.7<br /><br />Emitter size, µm 9*9<br /><br />Distance between transistors, mm 4<br /><br />Switching:<br /><br />contacts 1, µm 3*3<br /><br />space line Me 1, µm 9.0<br /><br />contacts 2, µm 4*4<br /><br />space line Me 2, µm 14.0
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Application, features:
Low-voltage transistors:<br /><br />NMOS: Vtn= 1.8 V, Usd >16 V<br /><br />PMOS: Vtp= 1.5 V, Usd >16 V<br /><br />NPN: h21e= 100-300<br /><br />Resistors in layer:<br /><br />PolySi 1= 20-30 Ohm/sq<br /><br /> <br /><br />High-voltage transistors :<br /><br />NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V<br /><br />PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V
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Process Description:
Number of masks, pcs. 15<br /><br />Min design rule,µm 2.8<br /><br />Substrate: Si/B-doped/ p-type/ Res 80<br /><br />Isolation: LOCOS<br /><br />P-well depth, µm 6.5<br /><br />N-well depth, µm 4.5<br /><br />NDMOS base depth, µm 2.4<br /><br />Gate SiO2, Å 600<br /><br />Interlayer dielectric – Medium temp. PSG, µm 0,6 <br /><br />Channel length (gate): N/PMOS, µm 2.0<br /><br />Contacts, µm 2.0x2.0<br /><br />Space line Me 1, µm 8<br /><br />Space line Me 2, µm 10
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Application, features:
MOSFET<br /><br />NMOS: Vtn=2÷4 V<br /><br />Umax= 60÷900 V
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Process Description:
Number of masks, pcs. 8<br /><br />Min design rule,µm 2.0<br /><br />Substrate: Si/Sb-doped/ n-type/Res 0,015; <br /><br /> Si/ As-doped/ n-type/ Res 0,003<br /><br />Epi layer:<br /><br />thickness 8÷75) µm<br /><br />Resistivity (0,67÷31,5) Ohm/cm<br /><br />Gate oxide (60÷100) nm<br /><br />Interlayer dielectric medium temp. oxide + BPSG <br /><br />Passivation PEoxide + PE SI3N4