200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors

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範圍	意義
Тип карточки товара	Сложная
Application, features	Small -scale integration analogue IC, VDD < 210 V NPN Vertical: bn =70 Uсе=50 V NDMOS: Vtn= 2.0 V, Usd >200 V PDMOS: Vtp= -1.0 V, Usd >200 V NMOS: Vtn= 1.5V, Usd >20V Resistors in layer: NPN base, Р-drain, PolySi. Capacitors: PolySi-Si (SiO2 900 Å) PolySi-Al (SiO2 1600 Å)
Process Description	Number of masks, pcs. 19 Min design rule,µm 4.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 12/ (100) Buried layers: Si/Sb-doped/ n-type/Thk 30/Res 5.5; Si/B-doped/ p-type/Thk 300/Res2.0 ; Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0; Isolation: p-n junction P-well depth, µm 6.5 NDMOS base depth, µm 3.0 Gate SiO2, Å 900 NPN p-base depth, µm 2.5 N+emitter depth, µm 0.8 Interlayer dielectric – medium temp. PSG 0,55mm +SIPOS 0.1µm + medium temp. PSG 1,1µm Channel length (gate): N/PDMOS, µm 6 Space line PolySi, µm 8 Contacts, µm Ø4 Space line Me, µm 12

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