1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate
1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate
- Application, features: Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA<br /><br />PMOS: <br /><br />Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
- Process Description: Number of masks, pcs. 9<br /><br />Design rules,µm 3,0-5,0<br /><br />Substrate: Si/P-doped/ n-type/Res 4.5<br /><br />P-well depth, µm 6-8<br /><br />Gate SiO2, Å 800<br /><br />Interlayer dielectric: medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm 3<br /><br />Space line PolySi, µm 10<br /><br />Contacts , µm 5<br /><br />Space line Me, µm 12
- Тип карточки товара: Сложная
- Application, features: Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA<br /><br />PMOS: <br /><br />Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
- Process Description: Number of masks, pcs. 9<br /><br />Design rules,µm 3,0-5,0<br /><br />Substrate: Si/P-doped/ n-type/Res 4.5<br /><br />P-well depth, µm 6-8<br /><br />Gate SiO2, Å 800<br /><br />Interlayer dielectric: medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm 3<br /><br />Space line PolySi, µm 10<br /><br />Contacts , µm 5<br /><br />Space line Me, µm 12