雙擴散金屬氧化物半導體工藝

雙擴散金屬氧化物半導體工藝

Field N DMOS transistors

  • Application, features: MOSFET

    Low-power

    Vtn= 0,6-3,0V

    Ubr=50-200V

    Pmax=1,0 Watt

     

    High-power

    Vtn= 2,0-4,0V

    Ubr=50-600V

    Pmax=200 Watt
  • Process Description: Number of masks, pcs.                                              7-9<br /><br />Min design rule,µm                                                      3.0<br /><br />Substrate:                        Si/Sb-doped/ n-type/Res 0,01<br /><br />Epi layer: <br /><br />Thickness                                                          (9÷42) µm<br /><br />Resistivity                                              (0,7÷16) Ohm/cm<br /><br />Gate oxide                                                    (42,5÷80) nm<br /><br />Interlayer dielectric -                        medium temp. PSG <br /><br />Passivation:                                               low temp. PSG 

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

  • Application, features: MOSFET<br /><br />NMOS: Vtn=2÷4 V<br /><br />Umax= 60÷900 V
  • Process Description: Number of masks, pcs.                                                8<br /><br />Min design rule,µm                                                    2.0<br /><br />Substrate:                  Si/Sb-doped/ n-type/Res 0,015; <br /><br />                                   Si/ As-doped/ n-type/ Res 0,003<br /><br />Epi layer:<br /><br />thickness                                                         8÷75) µm<br /><br />Resistivity                                     (0,67÷31,5) Ohm/cm<br /><br />Gate oxide                                                  (60÷100) nm<br /><br />Interlayer dielectric       medium temp. oxide + BPSG <br /><br />Passivation                                    PEoxide + PE SI3N4

Field P DMOS transistors

  • Av (V/mV) Min: 4
  • Battery Current, IBAT1 (max), nA: 4
  • Battery Supply Voltage, VBAT: 4
  • External Caps (mF): 4
  • Features: 3
  • Frequency, kHz: 2
  • FT, МHz: 1
  • Functions: 12H/24H: 1
  • Process Description: Number of masks, pcs.                                             7-9<br /><br />Min design rule,µm                                                     3.0<br /><br />Substrate:                      Si/B-doped/ p-type/Res 0,005<br /><br />Epi layer: <br /><br />thickness                                                        (15-34) µm<br /><br />Resistivity                                               (2÷21) Ohm/cm<br /><br />Gate oxide                                                  (42,5÷80) nm<br /><br />Interlayer dielectric                        medium temp. PSG <br /><br />Passivation:                                            low temp. PSG 
  • U меж.баз., В (max): 324
  • Ucc ЖКИ,В: 23423
  • Uds, В: 4324
  • Ui max, В: 324
  • Uo, В: 32423
  • Uref, В, (max): 423
  • Uref, В, (min): 423
  • The prototype: UT54ACS164245