CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer
CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer
- Application, features: Digital IC, highly-resistant,<br />Epitaxy = 3 V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >5 V<br /><br />PMOS: Vtр=-0.6 V, Usd >5 V
- Process Description: Number of photolithographies, pcs. 15<br /><br />Design rule, μm 0.35<br /><br />Substrate: 725KDB0,015(100)<br /><br />Epitaxial layer: 15KDB12<br /><br />2 retrograde wells<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm 1.05 μm<br /><br />Gate SiO2, Å 70<br /><br />Channel length<br /><br />NMOS/PMOS, μm 0.35<br /><br />N&P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I Ti/AlCu / Ti /TiN<br /><br />PolySi pitch, μm 0.8<br /><br />Contacts 1 (W-filled), μm ø 0.5<br /><br />Metal 1 pitch, μm 0.95<br /><br />Metal 2 Ti/AlCu<br /><br />Contacts 2 (W-filled), μm ø 0.5<br /><br />Metal 2 pitch, μm 1.1
- Тип карточки товара: Сложная
- Application, features: Digital IC, highly-resistant,<br />Epitaxy = 3 V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >5 V<br /><br />PMOS: Vtр=-0.6 V, Usd >5 V
- Process Description: Number of photolithographies, pcs. 15<br /><br />Design rule, μm 0.35<br /><br />Substrate: 725KDB0,015(100)<br /><br />Epitaxial layer: 15KDB12<br /><br />2 retrograde wells<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PC TEOS, μm 1.05 μm<br /><br />Gate SiO2, Å 70<br /><br />Channel length<br /><br />NMOS/PMOS, μm 0.35<br /><br />N&P LDD- drains<br /><br />Titanium silicide<br /><br />Metal I Ti/AlCu / Ti /TiN<br /><br />PolySi pitch, μm 0.8<br /><br />Contacts 1 (W-filled), μm ø 0.5<br /><br />Metal 1 pitch, μm 0.95<br /><br />Metal 2 Ti/AlCu<br /><br />Contacts 2 (W-filled), μm ø 0.5<br /><br />Metal 2 pitch, μm 1.1