5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers

5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers

5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers
  • Application, features: Medium-scale integration EEPROM, VDD:2,4 V… 6  V<br /><br /> <br /><br />NMOS: Vtn=(0,65+-0,25)V, <br /><br />Usd >=12 V<br /><br />PMOS: Vtр=-(0,8+-0,2)V,<br /><br />Usd ≤-12 V<br /><br /> <br /><br />HV- NMOS: Vtn=(0,45+0,15)V Usd³17 V<br /><br />HV- РMOS: Vtр=-(0,8+0,2)V    Usd ≤-16 V
  • Process Description: Number of masks, pcs.                                             17<br /><br />Design rule, µm                                                       1.6<br /><br />Substrate: Si/B-doped/p-type/Res 12               2 wells                            <br /><br />N/P-well depth, µm                                                 5/6<br /><br />Gate SiO2, Å                                                          425<br /><br />Tunnel SiO2, Å                                                       77<br /><br />Interlayer dielectric-1: Si3N4, Å                            350<br /><br />Interlayer dielectric -2: BPSG, Å                           7000<br /><br />Built-in transistors<br /><br />Channel length: NMOS/PMOS<br /><br />Low-voltage transistors, µm                                     2.4<br /><br />High- voltage transistors, µm                                    3.6<br /><br />Space line PolySi 1, µm                                           3.2     <br /><br />Space line PolySi 2, µm                                           4.2<br /><br />Contacts, mm                                                        Ø 1.2<br /><br />Space line Me, µm                                                   4.4
  • Тип карточки товара: Сложная
  • Application, features: Medium-scale integration EEPROM, VDD:2,4 V… 6  V<br /><br /> <br /><br />NMOS: Vtn=(0,65+-0,25)V, <br /><br />Usd >=12 V<br /><br />PMOS: Vtр=-(0,8+-0,2)V,<br /><br />Usd ≤-12 V<br /><br /> <br /><br />HV- NMOS: Vtn=(0,45+0,15)V Usd³17 V<br /><br />HV- РMOS: Vtр=-(0,8+0,2)V    Usd ≤-16 V
  • Process Description: Number of masks, pcs.                                             17<br /><br />Design rule, µm                                                       1.6<br /><br />Substrate: Si/B-doped/p-type/Res 12               2 wells                            <br /><br />N/P-well depth, µm                                                 5/6<br /><br />Gate SiO2, Å                                                          425<br /><br />Tunnel SiO2, Å                                                       77<br /><br />Interlayer dielectric-1: Si3N4, Å                            350<br /><br />Interlayer dielectric -2: BPSG, Å                           7000<br /><br />Built-in transistors<br /><br />Channel length: NMOS/PMOS<br /><br />Low-voltage transistors, µm                                     2.4<br /><br />High- voltage transistors, µm                                    3.6<br /><br />Space line PolySi 1, µm                                           3.2     <br /><br />Space line PolySi 2, µm                                           4.2<br /><br />Contacts, mm                                                        Ø 1.2<br /><br />Space line Me, µm                                                   4.4