3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers
  • Application, features: IC for telephony, customized IC,<br /><br />VDD 3 V… 5  V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >10 V<br /><br />PMOS: Vtр=-0.7 V, Usd >10 V
  • Process Description: Number of masks, pcs.                                   14 (16)<br /><br />Design rule,µm                                                    0.8<br /><br />Substrate:                        Si/ P-doped/n-type/Res 4.5<br /><br />                     or  Si/B-doped/ p-type/Res 12; 2 wells<br /><br />N/P-wells depth, µm                                           4/4<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PE (TEOS)                          1,05 µm<br /><br />Gate SiO2, Å                                                 130/160<br /><br />NMOS/PMOS channel length, µm                 0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                                    Ti/AlCu/Ti/TiN<br /><br />Space line PolySi,µm                                           1.9<br /><br />Contacts 1 (filled in by W), µm                         Ø 0.7<br /><br />Space line Me 1, µm                                             2.2<br /><br />Me2                                                               Ti/AlCu<br /><br />Contacts 2 (filled in by W),µm                        Ø 0.7<br /><br />Space line Me 2, µm                                             2.4
  • Тип карточки товара: Сложная
  • Application, features: IC for telephony, customized IC,<br /><br />VDD 3 V… 5  V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >10 V<br /><br />PMOS: Vtр=-0.7 V, Usd >10 V
  • Process Description: Number of masks, pcs.                                   14 (16)<br /><br />Design rule,µm                                                    0.8<br /><br />Substrate:                        Si/ P-doped/n-type/Res 4.5<br /><br />                     or  Si/B-doped/ p-type/Res 12; 2 wells<br /><br />N/P-wells depth, µm                                           4/4<br /><br />Interlayer dielectric:<br /><br />SACVD SiO2 + PE (TEOS)                          1,05 µm<br /><br />Gate SiO2, Å                                                 130/160<br /><br />NMOS/PMOS channel length, µm                 0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                                    Ti/AlCu/Ti/TiN<br /><br />Space line PolySi,µm                                           1.9<br /><br />Contacts 1 (filled in by W), µm                         Ø 0.7<br /><br />Space line Me 1, µm                                             2.2<br /><br />Me2                                                               Ti/AlCu<br /><br />Contacts 2 (filled in by W),µm                        Ø 0.7<br /><br />Space line Me 2, µm                                             2.4