8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers

8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers

8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers
  • Application, features: Analogue-digital  IC for TV-receivers, Ucc=8V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >12 V<br /><br />PMOS: Vtр=-0.9 V, Usd >12 V<br /><br />NPN vertical:<br /><br />bn =120    Uce=10 V<br /><br />PNP lateral:<br /><br />bp =45      Uce=13 V
  • Process Description: Number of masks, pcs.                                           26<br /><br />Design rule,µm                                                     0.8<br /><br />Substrate:                           Si/B-doped/ p-type/Res 3<br /><br />Epitaxy:                 Si/P-doped/ n-type/ Thk 2.4/ Res 4.5<br /><br />p-well depth with p+cc, µm                                   4.3<br /><br />n-well depth with n+cc, µm                                   4.3<br /><br />Gate SiO2, Å                                                        130<br /><br />Interlayer dielectric:                                         BPSG<br /><br />Interlevel dielectric:                           PEoxide+ SOG<br /><br />NMOS/PMOS channel length, µm                 0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                               Ti-TiN/Al-Si/TiN<br /><br />Me II                                                      Ti/Al-Si/TiN<br /><br />NPN emitter size, µm                                    1.2*3.2<br /><br />Space line PolySi 2,µm                                       1.8<br /><br />Contacts 1, µm                                                  Ø 0.9<br /><br />Space line Me 1, µm                                             2.2<br /><br />Contacts 2,µm                                                  Ø 0.9<br /><br />Space line Me 2, µm                                             2.4
  • Тип карточки товара: Сложная
  • Application, features: Analogue-digital  IC for TV-receivers, Ucc=8V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >12 V<br /><br />PMOS: Vtр=-0.9 V, Usd >12 V<br /><br />NPN vertical:<br /><br />bn =120    Uce=10 V<br /><br />PNP lateral:<br /><br />bp =45      Uce=13 V
  • Process Description: Number of masks, pcs.                                           26<br /><br />Design rule,µm                                                     0.8<br /><br />Substrate:                           Si/B-doped/ p-type/Res 3<br /><br />Epitaxy:                 Si/P-doped/ n-type/ Thk 2.4/ Res 4.5<br /><br />p-well depth with p+cc, µm                                   4.3<br /><br />n-well depth with n+cc, µm                                   4.3<br /><br />Gate SiO2, Å                                                        130<br /><br />Interlayer dielectric:                                         BPSG<br /><br />Interlevel dielectric:                           PEoxide+ SOG<br /><br />NMOS/PMOS channel length, µm                 0.9/1.0<br /><br />N&amp;P LDD- drains<br /><br />Me I                                               Ti-TiN/Al-Si/TiN<br /><br />Me II                                                      Ti/Al-Si/TiN<br /><br />NPN emitter size, µm                                    1.2*3.2<br /><br />Space line PolySi 2,µm                                       1.8<br /><br />Contacts 1, µm                                                  Ø 0.9<br /><br />Space line Me 1, µm                                             2.2<br /><br />Contacts 2,µm                                                  Ø 0.9<br /><br />Space line Me 2, µm                                             2.4